Processing system with shared translation lookaside buffer

Details Processing system with shared translation lookaside buffer Processing system with shared translation lookaside buffer

2001-08-17

2004-05-25

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S130000

Reexamination Certificate

active

06742103

ABSTRACT:

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to multi-processor architectures and, more particularly, to a shared translation lookaside buffer in a multi-processor architecture.
2. Description of the Related Art
Many new electronic devices make use of a multi-processor environment that includes DSPs (digital signal processors), MPUs (microprocessor units), DMA (direct memory access units) processors, and shared memories.
The types of tasks performed by a device often have specific real time constraints due to the signals that they are processing. For example, DSPs are commonly used in devices where video and audio processing and voice recognition are supported. These functions can be significantly degraded if part of the multi-processor system must suspend processing while waiting for an event to occur. Performing memory address translations from virtual address used by a task to physical addresses necessary to access the physical memory can be time consuming and degrade performance for a real-time task. To reduce the latencies caused by address translation, a TLB (translation lookaside buffer) is commonly provided as part of a MMU (memory management unit). The translation lookaside buffer caches recently accessed memory locations. At the beginning of a memory access, the TLB is accessed. When a TLB (translation lookaside buffer) cache does not contain the information corresponding to the current access (i.e., a TLB-“miss” or “page fault”), the information must be retrieved from tables (“table walking”), located in main memory. This operation takes tens to hundreds of microprocessor cycles. While the MMU is walking the tables, the operation of the core is blocked, resulting in degraded or errant performance of the processor.
In a multiprocessor system, several separate processing devices may be performing virtual address translation in order to access the physical memory. In one solution shown in
FIG. 1
, of the type used by the ARM MEMC
2
, a multiprocessor device
10
uses a shared TLB
12
accessible by multiple processing devices
14
(individually referenced as processing devices
14
a-c
). Each processing device
14
has a unique requester identifier that is concatenated to a virtual address to form a modified virtual address. The concatenation is performed in order to present unique virtual addresses to the shared TLB
12
, since the virtual address range used by the various processors that access the shared TLB
12
may otherwise overlap, thereby presenting a possibility that the wrong physical address may be retrieved from the TLB
12
.
If there is a miss in the shared TLB
12
, the virtual address is translated to a physical address through translation tables
16
(individually referenced as translation tables
16
a-c
in
FIG. 1
) in the physical memory
18
. The requester identifier in the concatenated address provides a starting base address in the external memory's translation table section. Thus, each potential requester has its own translation table under this approach, which is an inefficient use of memory and provides no flexibility in translating a virtual address.
Accordingly, there is a need for a flexible method and circuit for translating virtual addresses to physical addresses in a multiprocessor device.
BRIEF SUMMARY OF THE INVENTION
In the present invention, an integral multiprocessing device comprises a plurality of processing devices, where two or more of the processing devices operate respective operating systems. A shared translation lookaside buffer is coupled to the processing devices for storing information relating virtual addresses with physical addresses in a main memory. The shared translation lookaside buffer generates a fault signal if a received virtual address is not related to an entry in the shared translation lookaside buffer. Responsive to a fault signal, translation logic determines physical address information based on the received virtual address, and criteria relating to the virtual address
The present invention provides significant advantages over the prior art. First, the invention provides for flexible determination of a physical address. Second, the invention does not require separate translation tables for each processing device to be stored in the external memory.


REFERENCES:
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 5809522 (1998-09-01), Novak et al.
patent: 6157986 (2000-12-01), Witt
patent: 6665775 (2003-12-01), Maiyuran et al.
patent: 0 215 544 (1987-03-01), None
patent: 0 382 237 (1990-08-01), None
patent: 0 642 086 (1995-03-01), None
Advanced RISC Machines Limited 1990, MEMC2, Technical Reference Manual, Part No. 2201,391, Issue 1, Dec. 1990, pp. 1-12.

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