Processing system using cascaded latches in a transmission path

Details Processing system using cascaded latches in a transmission path Processing system using cascaded latches in a transmission path

1986-05-16

1990-03-06

Williams, Jr., Archie E.

Boots, shoes, and leggings

36492371, 3649265, 36493101, 36493111, 3649314, 3649397, 36494834, 364951, 3649501, 377 81, G06F 1300, G06F 938, G11C 1900

Patent

active

049071874

ABSTRACT:
A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.

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Adams, Jr., "Sequential Buffer Control", IBM TDB, vol. 14, No. 7, 12/71, pp. 2069-2070.

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