Processing system implementing variable page size memory...

Details Processing system implementing variable page size memory... Processing system implementing variable page size memory...

2011-03-29

2011-03-29

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S205000, C711SE12059, C711SE12061

Reexamination Certificate

active

07917725

ABSTRACT:
A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry.

REFERENCES:
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patent: 5918250 (1999-06-01), Hammond
patent: 6378059 (2002-04-01), Miyoshi
patent: 2002/0169936 (2002-11-01), Murphy
patent: 2004/0215918 (2004-10-01), Jacobs et al.
patent: 2006/0123197 (2006-06-01), Dunshea et al.
patent: 2008/0104362 (2008-05-01), Buros et al.
patent: WO 2006/106428 (2006-10-01), None

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