Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2006-12-05
2006-12-05
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S216000
Reexamination Certificate
active
07146490
ABSTRACT:
Generally, the present invention provides a processing system and method for indicating when there is a pending write to a general register of the processing system. The processing system of the present invention utilizes a plurality of general registers, a plurality of connections, a pipeline, a scoreboard, and hazard detection circuitry. The plurality of connections corresponds respectively with the general registers. The scoreboard maintains a plurality of bits such that each bit indicates whether there is a pending write to a corresponding general register. The scoreboard transmits to the hazard detection circuitry one of the bits that is indicative of whether a pending write to the one general register exists based on a value of the one bit and based on which of the connections is used to transmit the one bit. The hazard detection circuitry then detects whether a data hazard exists based on the one bit.
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Arnold Ronny Lee
Soltis Jr. Donald Charles
Coleman Eric
Hewlett--Packard Development Company, L.P.
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