Boots – shoes – and leggings
Patent
1981-10-22
1984-12-11
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 300, G06F 500
Patent
active
044882556
ABSTRACT:
There is described a processing register particularly adapted for use in digital processing systems to implement various digital functions as high order digital filters and other structures which presently require complicated integrated circuit arrangements.
The processing register operates in five modes which are a shift register mode with multiple fixed delays, a shift register with multiple fixed delays and a time slot interchanger, a shift register mode with an alternating word pair interchanger, a programmable delay shift register and as a discrete fourier transform preprocessing module.
The processing register is particularly adaptable to operate with a high speed multiplier to implement various digital processing functions. In order to accommodate mode operation the processing register contains a main shift register and a computation register which are under the control of a control register which register accepts a control input word having bits thereof indicative of a particular mode of operation.
The processing register further includes an independent storage register which shares overflow operation with the main storage register and which register can also be controlled by the control word during certain of the above described modes of operation. In order to provide flexibility the processing register contains a 1 to 2 multiplexer which is programmable according to the status of a second control word. The multiplexer register can operate in conjunction with the main and independent registers during certain other modes of operation. In order to accommodate the multiple modes of operation there is further included a sum and difference register whose inputs can be selected during mode operation to enable one to couple sum and difference digital signals to the multiplexer or to the inputs of the main and independent storage registers.
In the configuration described data computation and control of the processing register is synchronized with the clock input and a word sync signal which signals define the relationship of all operations and thus enable one to perform complicated digital functions in a simple and reliable manner.
REFERENCES:
patent: 4130883 (1978-12-01), Hazelton
patent: 4291374 (1981-09-01), Dlugos
patent: 4374429 (1983-02-01), Cannon et al.
Chitsaz Sirus
Krisher Dale L.
International Telephone and Telegraph Corporation
Meagher Thomas F.
Mills John G.
Morris Jeffrey P.
O'Halloran John T.
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