Processing method, chip set and controller for supporting...

Details Processing method, chip set and controller for supporting... Processing method, chip set and controller for supporting...

2005-09-06

2005-09-06

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S262000, C710S268000

Reexamination Certificate

active

06941398

ABSTRACT:
A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

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PCI Local Bus Specification 2.2, Dec. 18, 1998, Section 6.8.

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