Processing method and apparatus for implementing systolic...

Details Processing method and apparatus for implementing systolic... Processing method and apparatus for implementing systolic...

2007-08-21

2007-08-21

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S019000, C712S024000, C711S170000

Reexamination Certificate

active

10511504

ABSTRACT:
The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data, wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.

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J. Kang Van Der Werf et al., “Mapping Array Communication onto FIFO Communication-Towards an Implementation”, Proceedings 13th Int'l Symposium on Systems Synthesis, pp. 207-213, Published: Los Angeles, CA.

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