Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent
1997-11-12
2000-10-10
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
711150, 710 56, G06F 1202
Patent
active
061311510
ABSTRACT:
Methods and apparatus are described for managing high-bandwidth incoming digital data streams, such as MPEG encoded data streams, while reducing memory requirements. Frames of incoming data are divided into smaller slices, for example four slices per frame. A sequencing memory is used to store frame store memory addresses pointing to locations in the frame store buffer where slices of data are stored. As incoming data is stored in the frame buffer, corresponding start location addresses are stored in the sequencing memory, and corresponding bits in a status register are marked as busy. Conversely, as data is read out of the frame store for decoding or reconstruction, the corresponding bit in the status register is changed to the free status, as each slice of data is processed. This procedure and corresponding architecture reduces frame store memory requirements.
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Chan Eddie P.
Ellis Kevin L.
LSI Logic Corporation
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