Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-06-18
2003-01-07
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S151000, C710S244000, C710S112000
Reexamination Certificate
active
06505276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet-type memory Large Scale Integration circuit (LSI) having a packet-type memory bus and interface to be preferably used for a large-capacity memory LSI, particularly to a memory system of a processing-function-provided packet-type memory LSI configured for adding a processing function to a packet-type memory LSI and a method for controlling the memory system.
2. Description of the Prior Art
Japanese Patent Laid-Open No. 10-049428 specification (Japanese Patent Application No. 08-204668) discloses an art for constituting a processing-function-provided memory system by using a memory LSI and a processing-function-provided memory LSI.
Moreover, relating to the above art, Japanese Patent Application No. 09-097587 which was applied prior to this application but which was not released when this application was applied discloses an art for configuring a similar processing-function-provided memory system by particularly using a packet-type memory LSI and a processing-function-provided packet-type memory LSI.
In this case, a packet-type memory LSI represents a memory LSI for performing memory access by using a packet such as a Direct Rambus DRAM (Direct Rambus Dynamic Random Access Memory) (referred to as DRDRAM) or a Synchronous-Link DRAM (Synchronous-Link Dynamic Random Access Memory) (referred to as SLDRAM) and it is described in detail in “Direct Rambus Technology: The New Main Memory Standard” on pp. 18-28 and “SLDRAM: High-Performance, Open-Standard Memory” on pp. 29-39 in November/December 1997 issue of Journal for “IEEE Micro.”
Moreover, a coprocessor-contained packet-type memory LSI represents a packet-type memory LSI configured by containing a coprocessor in an LSI. As for this specification, LSIs including those having a processing function other than a coprocessor are referred to as “processing-function-provided packet-type memory LSI.”
In general, a memory system is configured by arranging a plurality of memory LSIs but it has only a function for storing the data used for processing. However, the processing-function-provided memory system disclosed in the official gazette of Japanese Patent Laid-Open No. 10-049428 specification is configured by using a memory LSI and a processing-function-provided memory LSI, which makes it possible to perform processing by a processing-function-provided memory LSI in the processing-function-provided memory system.
Moreover, the processing-function-provided packet-type memory system disclosed in the above Japanese Patent Application No. 09-097587 is configured by using a packet-type memory LSI and a processing-function-provided packet-type memory LSI, which controls execution of processing by the processing-function-provided packet-type memory LSI by using a packet instead of using the above mechanism of making memory access to a packet-type memory LSI by using a packet.
Moreover, Japanese Patent Laid-Open No. 61-91757 specification discloses a data transfer controller. The data transfer controller is configured of two controllers connected to each other by a bi-directional data bus, a plurality of control lines and an input/output unit connected to the bi-directional data bus which transfers data to and from only one of the two controllers. During data transfer for each unit-length data is performed through the bi-directional data bus while asynchronously confirming an other-controller's response signal to one-controller's request signal through the control line between the two controllers, one controller can transfer data to and from the input/output unit through the bi-directional data bus when the other controller switches transfer modes for the bi-directional data bus. Moreover, a monitoring signal line for inverting the logical state of a monitoring signal by responding start or end of data transfer between the two controllers is used as the control line and at least the other of the two controllers has decision means for deciding the validity of the logical state of the monitoring signal.
Furthermore, the official gazette of Japanese Patent Laid-Open No. 63-88666 specification discloses a bus adjustment controller. The bus adjustment controller is provided with a microprocessor not containing a bus-using-right adjustment function and a direct memory access controller for obtaining or resigning the bus-using right through the handshake system between a bus-using request signal and a bus-using permission signal to adjust the competition for bus-using produced between the microprocessor and the direct memory access controller.
Furthermore, Japanese Patent Laid-Open No. 63-106035 specification discloses a semiconductor file memory apparatus. The semiconductor file memory comprises an auxiliary memory using a semiconductor memory connected to a computer system to store and write/read or read data wherein the semiconductor file memory is a large-capacity semiconductor file memory configured from a Small Computer Systems Interface (SCSI) protocol control circuit, a microprocessor, a Direct Memory Access (DMA) control circuit, a bus drive, and a semiconductor memory provided with an address decoding circuit so that data can be transferred at a high speed when connected to the SCSI bus.
Furthermore, Japanese Patent Laid-Open No. 2-120961 specification discloses an invention related to an inter-memory data transfer system. The system comprises an information processor configured of at least a processor, a memory, and a DMA controller are connected by a local bus to a plurality of arithmetic units, are connected by a mutual connection line wherein the DMA controller in each arithmetic unit has at least a function for obtaining the bus-using right from the processor in the arithmetic unit, a function for resigning the bus-using right, a function for reading or writing data in a memory through the bus, a function for providing an instruction for the DMA controllers connected to other arithmetic units, a function for receiving instructions from the DMA controllers of the arithmetic units, a function for executing instructions supplied from DMA controllers of the arithmetic units, and a function for reading or writing data from or in memories of these arithmetic units and moreover, these functions can be separately and independently operated. Moreover, the DMA controller of a first arithmetic unit makes it possible to mutually perform data read and write operations between the memory of the first arithmetic unit and the memory of a second arithmetic unit via the mutual connection line with the processor of the first arithmetic unit and the processor of the second arithmetic unit separated from each bus.
Furthermore, Japanese Patent Laid-Open No. 8-235106 specification discloses an interfacing method and a system for an upgrade processor. This provides a method and a system for interfacing an upgrade processor and a data processing system having data bus widths different from each other. Specifically, the data processing system has a first processor having an m-byte data width, an n-byte data bus (m≧n), and a second processor connected to the bus to execute bus transaction by using an n-byte data packet. An adapter electrically connected between the first processor and the bus converts an n-byte data packet input from the bus into an m-byte data packet and an m-byte data packet input from the first processor into an n-byte data packet. Thereby, the first processor can transfer data to and from the bus by using the m-byte data packet. The second mode is a method and a system for adjusting the portion between two buses and masters having bus-obtaining protocols different from each other.
As for the memory system disclosed in the above prior application, a processing-function-provided memory system, particularly a processing-function-provided packet-type memory system is constituted by directly using a conventional memory bus, particularly, the conventional configuration of a packet-type memory bus. This is due to the following reason.
In genera
Bataille Pierre-Michel
Kim Matthew
NEC Corporation
Whitham Curtis & Christofferson, PC
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