Processing full exceptions using partial exceptions

Details Processing full exceptions using partial exceptions Processing full exceptions using partial exceptions

1999-07-30

2004-02-10

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S233000

Reexamination Certificate

active

06691223

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to exception generation.
2. Description of Related Art
Modern microprocessors have been developed with advanced architectures to support demanding applications such as scientific computations, multimedia, imaging, and graphics. Recently, there is a trend in designing processors with parallel processing capability. An example of parallel architectures is single-instruction-multiple-data (SIMD) architecture.
An SIMD architecture typically has computational units that can process multiple data items in parallel or simultaneously. For example, an SIMD machine may define a floating-point (FP) packed data type that contains four 32-bit single-precision (SP) numbers packed as a 128-bit quantity. In this architecture, the SIMD machine has an execution engine that executes on all four SP numbers simultaneously.
Exceptions are conditions that indicate some abnormal behavior or boundary conditions of the machine. In computational units, exceptions are typically generated as a result of boundary conditions, incorrect operands or results. In SIMD machines, full exceptions are to be generated for all the data items involved in the computations.
When a processor is designed to be compatible with an SIMD machine, the processor should maintain the same full exception generation to ensure correct result.
Therefore there is a need in the technology to provide a simple and efficient method to process full exceptions as provided by an SIMD machine.
SUMMARY
The present invention is a method and apparatus for processing full exceptions in a partial parallel processor operating on parallel operands which form into N groups. The method comprising: (a) generating P partial exception states for P partial exceptions from the partial parallel processor operating on the N groups of the parallel operands; the P partial exceptions correspond to the full exceptions; and (b) handling the P partial exceptions based on the P partial exception states.


REFERENCES:
patent: 5949996 (1999-09-01), Atsushi
patent: 6006030 (1999-12-01), Dockser
patent: 6122729 (2000-09-01), Tran
patent: 6282636 (2001-08-01), Yeh et al.
patent: 6378067 (2002-04-01), Golliver et al.

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