Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate
2006-04-11
2006-04-11
Chace, Christian P. (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
C711S137000, C712S207000, C712S237000
Reexamination Certificate
active
07028159
ABSTRACT:
An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.
REFERENCES:
patent: 5146578 (1992-09-01), Zangenehpour
patent: 5377336 (1994-12-01), Eickemeyer et al.
patent: 5652858 (1997-07-01), Okada et al.
patent: 5680637 (1997-10-01), Hotta et al.
patent: 5689679 (1997-11-01), Jouppi
patent: 5732242 (1998-03-01), Mowry
patent: 5740399 (1998-04-01), Mayfield et al.
patent: 5758119 (1998-05-01), Mayfield et al.
patent: 6131145 (2000-10-01), Matsubara et al.
patent: 6381679 (2002-04-01), Matsubara et al.
patent: 6598126 (2003-07-01), Matsubara et al.
patent: 6598127 (2003-07-01), Matsubara et al.
Chen, “A Performance Study of Software and Hardware Data Prefetching Schemes,” Proceedings of the 2nd Annual International Symposium on Computer Architecture, Apr. 18-21, 1994, pp. 223-232.
Chi, et al, “Reducing Data Access Penalty Using Intelligent Opcode Driven Cache Prefetching”, Proceedings Intel. Conf. On Computer Design: VLSI in Computers and Processors, IEEE Compute. Soc. Press, pp. 512-517 (conf. Date Oct. 2-4, 1995).
Chi et al, “Complier Driven Data Cache Prefetching for High performance Computers,” Proceedings of 1994 IEEE Region 10's Ninth Annual Intel,Conf.,Aug. 22-26, 1994, pp. 274-278, vol. 1.
D. Callahan et al, “Software Prefetching”, Proceedings of the 4thInternational Conference on Architectual Support for Programming Languages and Operating Systems, Apr. 1991, pp. 40-52.
Bennett, et al, “Prefetching in a Multilevel Memory Hierarchy,” IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, p. 88.
“Cache Prefetching Scheme with Increased Timeliness and Conditional Prefetches for a two-level cache structure”, IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, pp. 375-376.
Imori Hiromitsu
Kurihara Toshihiko
Matsubara Kenji
Chace Christian P.
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
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