Processing architecture having an array bounds check capability

Details Processing architecture having an array bounds check capability Processing architecture having an array bounds check capability

2005-05-10

2005-05-10

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Logic operation instruction processing

C712S222000, C712S227000

Reexamination Certificate

active

06892295

ABSTRACT:
According to the invention, a method for processing data related to an array of elements is disclosed. In one embodiment, a method for processing data related to an array of elements is disclosed. In the process, a first value is loaded from a first location, and a second value is loaded from a second location. The first and second values are compared to each other. A predetermined value is optionally stored at a destination based upon the outcome of the comparison.

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