Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-06-07
2002-04-09
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000
Reexamination Certificate
active
06370557
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a processing apparatus and a method of the same. 2. Description of the Related Art
A processing apparatus which receives as its inputs positive binary data A, B, and C and performs an operation “(A−B)×C”, is known in the art.
Below, an explanation will be made of a processing apparatus of the related for performing the operation “(A−B)×C”.
FIG. 6
is a view of the configuration of the processing apparatus of the related for performing the operation “(A−B)×C”.
As shown in
FIG. 6
, the processing apparatus
1
has a subtracter
2
and a multiplier
3
and performs the operations “(A−B)×C” by using the 4-bit data A, B, and C.
The processing apparatus
1
, for example, performs the subtraction of the 4-bit data A and the 4-bit data B at the subtracter
2
and the multiplication of the signed 5-bit subtraction result Y and the 5-bit data C with a most significant bit (MSB) having a logical value “0” due to code expansion at the multiplier
3
. Then, the multiplication result of the multiplier
3
becomes the result of the operation “(A−B)×C”.
As the subtracter
2
, for example, as shown In
FIG. 7. a
ripple carry type adder comprised of full adders (FA)
10
0
,
10
1
,
10
2
, and
10
3
connected in series, is used.
In this subtracter
2
, “1” for finding a complement of 2 is Input to a Ci (Carry In) terminal of the full adder
10
1
performing the operation corresponding to the least significant bit (LSB). Further, the bit data A
0
to A
3
of the data A are Input to the full adders
10
0
to
10
3
and the bit data B
0
to B
3
of the data B are Input via inverters
11
0
to
11
3
. Then, bit data Y
0
to Y
3
of the 4-bit result Y are output from s terminals of the full adders
10
0
to
10
3
and bit data Y
4
indicating the sign of the subtraction result Y Is output from a CO (Carry Out) terminal of the full adder
10
3
.
Note that, as the full adders
10
1
to
10
3
, as shown In
FIG. 8
, use is made of a general full adder constituted by combining AND circuits
15
1
, and
15
2
, OR and
17
2
. At the full adders
10
1
to
10
3
, bit data input through an in
1
terminal, in
2
terminal, and Ci (Carry in ) terminal are added, the carry of the addition result Is output from the CO (Carry out) terminal, and sum data Is output from the S terminal.
Next, an explanation will be made of the configuration of the multiplier
3
shown In FIG.
6
.
FIG. 9
Is a view for explaining a complement multiplication of 2 according to the Baugh Wooly method adopted by the multiplier
3
.
A
FIG. 10
is a view of the configuration of the multiplier
3
performing the complement multiplication of 2 shown in FIG.
9
.
As shown in
FIG. 10
, the multiplier
3
has a partial product adder circuit
20
and a final stage adder circuit
30
.
The partial product adder circuit
20
adopts the Wallace-tree method and has AND circuits
21
0
to
21
24
, full adders
22
1
to
22
13
, half adders
23
1
to
23
3
, and inverter circuits
24
1
to
24
11
.
Further, the final adder circuit
30
adopts the Ripple Carry method and has full adders
22
14
to
22
19
and half adders
23
4
and
23
5
.
Here, the full adders
22
14
to
22
19
have the configuration shown in
FIG. 8
mentioned above. Further, as the half adders
23
1
to
23
3
, as shown in
FIG. 11
, provision is made of an AND circuit
15
3
and an XOR circuit
17
3
, data input through the in terminal and the in
2
terminal are added, the carry of the related addition result is output from the CO (Carry Out) terminal, and the sum data is output from the S terminal.
At the multiplier
3
, the AND circuits
21
1
to
21
24
of the partial product adder circuit
20
use the bit data Y
0
, Y
1
, Y
2
, Y
3
, and Y
4
of the subtraction result Y from the subtracter
2
and the bit data C
0
, C
1
, C
2
, C
3
, and 0 with an MSB having the logical value “0” due to code expansion for the partial products shown in FIG.
9
. Then, the partial products are added at the full adders
22
1
to
22
19
and the half adders
23
1
to
23
5
of the partial product adder circuit
20
and the final stage adder circuit
30
including a carry from a lower digit for every digit. By this, sum data output from the output terminal of the AND circuit
21
0
and s terminals of the half adders
23
1
and
23
4
, the full adders
22
14
,
22
15
,
22
16
,
22
17
,
22
18
, and
22
19
, and the half adder
23
5
become bit data S
0
, S
1
, S
2
, S
3
, S
4
, S
5
, S
6
, S
7
, S
8
, and S
9
of the 10-bit result S.
Summarizing the problem to be solved by the invention, in the processing apparatus
1
of the related art mentioned above, as shown in FIG.
7
and
FIG. 10
, there is a disadvantage that there are the full adders
10
0
to
10
3
, AND circuits
21
0
to
21
24
, full adders
22
1
to
22
19
, half adders
23
1
to
22
5
, and inverter circuits
24
1
to
24
11
and the size of the circuit becomes large.
Namely, in the processing apparatus
1
, as shown in
FIG. 1
, in order to perform the subtraction at the subtracter
2
, when using 4-bit data A and B, the result thereof becomes 5 bits, including the sign bit. As a result, at the multiplier
3
, it is necessary to perform the multiplication of 5 bits and the size of the circuit becomes large.
Further, in the processing apparatus
1
of the related art mentioned above, the critical path of the operation becomes the full adders
10
0
to
10
3
, half adder
23
4
, full adders
22
14
,
22
15
,
22
16
,
22
17
,
22
18
, and
22
19
, and the half adder
23
5
, so there is a disadvantage that the processing time becomes long.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a processing apparatus capable of reducing the size of the circuit performing the operation “(A−B)×C”.
Another object of the present invention is to provide a processing apparatus capable of shortening the processing time of the operation “(A−B)×C”.
According to a first aspect of the present invention, there is provided a processing apparatus for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A
i
(i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B
i
(i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C
j
(j=0, 1, . . . n−1), said processing apparatus comprising: a bit data selecting means for receiving as input the bit data A
i
, B
i
, and C
j
, and outputting the bit data A
i
when C
j
equals to a first logical value or the bit data B
i
when data C
j
equals to a second logical value in response to data C
j
with respect to all combinations of the natural numbers i and J and an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.
The processing apparatus of the present invention performs the operation “(A−B)×C” based on the following equation (1):
S
=
(
∑
j
=
0
j
=
n
-
1
∑
i
=
0
i
=
n
-
1
·
(
A
j
·
C
j
|
B
i
·
C
_
j
)
)
-
2
n
×
B
+
B
(
1
)
That is, in the processing apparatus of the present invention, each of the plurality of bit data selecting means outputs the bit data A
i
when the input C
j
is the logical value “1” and outputs the bit data B
i
when C
j
is the logical value “0” among the input bit data A
i
and B
i
.
Next, the adding means adds the bit data output from the bit data selecting means to the (i+j)th bit by adding for each bit the bit data output from the bit data selecting means, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, the data B, and the carry data carried from a lower bit.
Preferably, it further
Kananen Ronald F.
Malzahn David H.
Rader Fishman & Grauer
Sony Corporation
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