Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-07-13
2002-04-30
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S401000, C327S384000, C326S027000, C326S087000
Reexamination Certificate
active
06380770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to output drivers and, more particularly, to a low ground bounce and low power supply bounce output driver with dual, interlocked, asymmetric delay lines.
2. Description of the Related Art
A CMOS digital output driver is a well known circuit that outputs a logic high or a logic low to a load capacitance by charging or discharging the load capacitance. In practice, several output drivers are often connected to the same ground (GND) line and the same power supply (VCC) line.
One of the problems associated with connecting several noisy (high di/dt) output drivers to the same ground line is that significant ground bounce (switching noise) can be generated when many (or all) of these output drivers discharge their load capacitances at the same time.
FIG. 1
shows a circuit diagram that illustrates a portion of a conventional output driver circuit
100
. As shown in
FIG. 1
, driver circuit
100
includes a series of high di/dt output drivers driver#
1
-driver#N which each have a p-channel transistor
110
and an n-channel transistor
112
.
Each p-channel transistor
110
has a source connected to a power supply VCC, a drain connected to is an output pad
114
, and a gate. Each n-channel transistor
112
has a source connected to a common ground line
116
, a drain connected to the drain of the p-channel transistor
110
, and a gate.
During normal operation, when a single output driver is switched from a logic high to a logic low, a time varying current i(t)
D
from the load capacitance is placed on common ground line
116
as a result of the load capacitance being discharged. Similarly, when all of the output drivers driver#1—driver#N are simultaneously switched from a logic high to a logic low, a large time varying discharge current, which is the sum of the individual time varying discharge currents i(t)
D
, is placed on common ground line
116
.
The large time varying discharge current causes the voltage on common ground line
116
to vary due to the inductance of common ground line
116
(which is shown as an inductor L). As shown in EQ. 1, the voltage variation VLG on common ground line
116
is defined as follows:
VLG=L*N
(
di
(
t
)
D
/dt
) EQ. 1
where L represents the inductance of common ground line
116
(including package inductance and bondwire inductance), N represents the number of drivers driver#
1
-driver#N that are discharging their load capacitances at the same time, and di(t)/dt represents the time varying discharge current i(t)
D
through a single driver.
Thus, as shown in EQ. 1, extremely high ground bounce (switching noise) can be generated when several drivers driver#
1
-driver#N are switched from a logic high to a logic low at the same time.
Similarly, a significant power supply bounce (switching noise) can be generated when several noisy (high di/dt) output drivers charge their load capacitances from the same power supply line at the same time.
FIG. 2
shows a circuit diagram that illustrates a portion of a conventional output driver circuit
200
. Output driver circuit
200
is similar to output driver circuit
100
and, as a result, utilizes the same reference numerals to designate the structures which are common to both circuits.
In addition to the elements of circuit
100
, output driver circuit
200
also includes a common power supply line
210
which is connected to the source of the p-channel transistor
110
in each of the output drivers driver#
1
-driver#N.
During normal operation, when a single output driver is switched from a logic low to a logic high, a time varying charge current i (t)
c
from the VCC power supply is placed on common power supply line
210
, as a result of the load capacitance being charged. Similarly, when all of the output drivers driver#
1
-driver#N are simultaneously switched from a logic low to a logic high, a large time varying charge current from the VCC power supply is placed on common power supply line
210
. This time varying current is the sum of the individual time varying charge currents i(t)
c
.
The large time varying current causes the voltage on common power supply line
210
to also vary due to the inductance of line
210
(shown as inductor L). As shown in EQ. 2, the voltage variation VLV on common power supply line
210
is defined as follows:
VLV=L*N
(
di
(
t
)
c
/dt
) EQ. 2
where L represents the inductance of power supply line
210
(including package inductance and bondwire inductance), N represents the number of drivers driver#
1
-driver#N that are charging their load capacitances at the same time, and di(t)/dt represents a single time varying charge current i(t)
c
.
Thus, as shown in EQ. 2, extremely high power supply bounce (switching noise) can be generated when several drivers driver#
1
-driver#N are switched from a logic low to a logic high at the same time.
The parent invention minimized ground bounce and power supply bounce with an output driver that utilized a number of p-channel driver transistors in lieu of a single p-channel driver transistor, and a number of n-channel driver transistors in lieu of a single n-channel driver transistor.
In addition, the output driver of the parent invention utilized a first delay line to sequentially turn on and turn off of the p-channel driver transistors, and a second delay line to sequentially turn on and turn off of the n-channel driver transistors. In addition, the p-channel and n-channel driver transistors are turned on slowly, and turned off quickly.
To further minimize bounce in the parent invention, none of the p-channel driver transistors are preferably turned on when an n-channel driver transistor is turned on, and none of the n-channel driver transistors are preferably turned on when a p-driver channel transistor is turned on. One problem with the parent invention, however, is that it is difficult to set up the timing to insure that the p-channel and n-channel driver transistors are not turned on at the same time.
Thus, there is a need for an output driver that slowly turns on and quickly turns off the p-channel driver transistors in sequence, slowly turns on and quickly turns off the n-channel driver transistors in sequence, and insures that the p-channel and n-channel driver transistors are not turned on at the same time.
SUMMARY OF THE INVENTION
Conventionally, noisy (high di/dt) output drivers can generate significant ground bounce and power supply bounce whenever they switch from high to low or from low to high at the same time. The present invention reduces ground bounce and power supply bounce with an output driver that utilizes a number of p-channel driver transistors in lieu of a single p-channel driver transistor, and a number of n-channel driver transistors in lieu of a single n-channel driver transistor.
In addition, the output driver of the present invention utilizes dual, interlocked, asymmetric delay lines to slowly turn on and quickly turn off the p-channel driver transistors in sequence, and slowly turn on and quickly turn off the n-channel driver transistors in sequence. In accordance with the present invention, the dual, interlocked, asymmetric delay lines insure that the p-channel and n-channel driver transistors are not turned on at the same time.
The present invention is especially useful for implementing fast, high current output drivers that must drive high capacitive loads, such as PCI bus drivers. In addition, mixed signal (analog/digital) chips will greatly benefit from the reduced switching noise (bounce) that occurs on the VCC and ground lines.
An output driver in accordance with the present invention includes a first delay line. The first delay line has a plurality of first delay stages that output a corresponding plurality of delayed first signals. The first delay line is connectable to receive a number of first control signals, and connected to receive a number of first feedback signals. The output driver also includes a plurality of fir
National Semiconductor Corporation
Nguyen Long
Pillsbury & Winthrop LLP
Tran Toan
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