Process yield learning

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

Other Related Categories

C716S030000, C716S030000, C716S030000, C716S030000

Type

Reexamination Certificate

Status

active

Patent number

07114143

Description

ABSTRACT:
A method for producing yield enhancement data from integrated circuits on a substrate. A database of defects on the substrate is compared to a database of design information for the integrated circuits. The defects on the substrate are associated with classes of design information to produce the yield enhancement data.

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patent: 6542830 (2003-04-01), Nakazato et al.
patent: 6553329 (2003-04-01), Balachandran
patent: 6701477 (2004-03-01), Segal
patent: 6707936 (2004-03-01), Winter et al.
patent: 2005/0066294 (2005-03-01), Templeton et al.
Bichebois et al.,“Analysis of Defect to Yield Correlation of Memories: Method, Algorithms and Limits”, Oct. 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Proceedings pp. 44-52.
Cheema et al.,“Wafer Back Side Inspection Applications for Yield Protection and Enhancement”, May 2002, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Paper Digest pp. 64-71.

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