Process to reduce gate edge drain leakage in semiconductor...

Details Process to reduce gate edge drain leakage in semiconductor... Process to reduce gate edge drain leakage in semiconductor...

2005-02-15

2005-02-15

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257SE21618

Reexamination Certificate

active

06855984

ABSTRACT:
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.

REFERENCES:
patent: 6057184 (2000-05-01), Brown et al.
patent: 6097068 (2000-08-01), Brown et al.
patent: 6410410 (2002-06-01), Feudel et al.
patent: 6509586 (2003-01-01), Awano

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