Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-06-27
2002-02-12
Niebling, John A. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S788000, C438S798000, C438S520000
Reexamination Certificate
active
06346488
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a process for treating a film of low dielectric constant (k) dielectric material of an integrated circuit structure on a semiconductor substrate by implanting the film with hydrogen ions to inhibit subsequent cracking of the film of low k dielectric material and to further reduce the dielectric constant of the low k dielectric film.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U. K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicone oxide which is annealed at 400° C. to remove moisture. While the use of carbon-doped silicon oxide dielectric materials, as well as other materials mentioned in the Peters article, has resulted in a reduction in capacitance in integrated circuit structures utilizing such materials, a problem has been noted in the processing of such low k dielectric materials. After formation of a film of low k dielectric material, it is customary to subject the film to an anneal to drive off any moisture which may have formed during the process of making and depositing the low k film. The low k dielectric film has been noted to have a tendency to develop cracks during such exposure to elevated temperatures. Presumably the cracking results from stresses developed in the film during polymerization and structure formation which is accelerated by heating. The removal of water from the film during the heating step and resultant increase in film porosity may result in film shrinkage. The differences between the physical properties (thermal expansion coefficients, rigidity, etc.) of the low k film and the substrate may also contribute to the cracking problem.
In any event, the cracking of films of low k dielectric material during subsequent exposure to high temperatures, such as found in annealing processes (e.g., 400° C. or higher), results in an unacceptable reduction in yield which must be addressed. It would, therefore, be desirable to provide a process for treating such films of low k dielectric material to inhibit cracking of such films upon exposure to annealing temperatures.
It has been proposed by others to treat the film of low k dielectric material in a hydrogen plasma to enhance the resistance to cracking. However, such plasma treatment has been found to be only superficial, affecting only the surface and a very shallow depth of the film. Apparently, normal plasma conditions are insufficient to affect the deeper levels or regions of the low k film of dielectric material. The computation of the penetration depth of the dopant peak Rp of H
+
ions with the energy ~500 eV (the average ion energy of hydrogen ions in a plasma generated in a diode mode) into amorphous silicon oxide (SiO
2
) film shows that the Rp is near 100 Angstroms (Å). In reality, the dominant ions in a hydrogen plasma are H
2
+
ions, and the penetration depth of these ions into SiO
2
will be even smaller. Therefore the bulk of low k dielectric films, which may range from 4000 Å to 8,000 Å in thickness, cannot be treated by a conventional hydrogen plasma.
Chu et al., in an article entitled “A New Way To Make SOI Wafers”, published in the May 1997 edition of Solid State Technology, describes the use of plasma immersion ion implantation (PIII) for implanting oxygen in the formation of SOI (silicon-on-insulator) wafers, and further describes the implantation of helium and hydrogen into the silicon wafer by PIII to form a plane of implanted ions in the wafer along which cracking of the wafer will occur.
SUMMARY OF THE INVENTION
A film of low k dielectric material formed on a semiconductor substrate is treated to inhibit subsequent cracking of the film of low k dielectric material, and to further reduce the dielectric constant of the low k dielectric material by implanting the film of low k dielectric material with hydrogen ions by applying a negative DC bias to the semiconductor substrate in the presence of a plasma in hydrogen-containing gases. The semiconductor substrate, with the film of low k dielectric material thereon, is mounted on an electrically conductive substrate support in a reactor and a negative DC bias is applied to the semiconductor substrate by connecting the electrically conductive substrate support to a source of negative DC bias while hydrogen ions are generated by the plasma in the reactor to thereby cause hydrogen ions to implant into the film of low k dielectric material on the semiconductor substrate to thereby inhibit cracking of the low k film of dielectric material, and to further reduce the dielectric constant of the film.
REFERENCES:
patent: 3012861 (1961-12-01), Ling
patent: 3178392 (1965-04-01), Kriner
patent: 3832202 (1974-08-01), Ritchie
patent: 3920865 (1975-11-01), Läufer et al.
patent: 4705725 (1987-11-01), Glajch et al.
patent: 4771328 (1988-09-01), Malaviya et al.
patent: 5194333 (1993-03-01), Ohnaka et al.
patent: 5314845 (1994-05-01), Lee et al.
patent: 5364800 (1994-11-01), Joyner
patent: 5376595 (1994-12-01), Zupancic et al.
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5558718 (1996-09-01), Leung
patent: 5559367 (1996-09-01), Cohen et al.
patent: 5580429 (1996-12-01), Chan et al.
patent: 5628871 (1997-05-01), Shinagawa
patent: 5675187 (1997-10-01), Numata et al.
patent: 5688724 (1997-11-01), Yoon et al.
patent: 5858879 (1999-01-01), Chao et al.
patent: 5864172 (1999-01-01), Kapoor et al.
patent: 5874367 (1999-02-01), Dobson
patent: 5874745 (1999-02-01), Kuo
patent: 5882489 (1999-03-01), Bersin et al.
patent: 5904154 (1999-05-01), Chien et al.
patent: 5915203 (1999-06-01), Sengupta et al.
patent: 5939763 (1999-08-01), Hao et al.
patent: 6025263 (2000-02-01), Tsai et al.
patent: 6028015 (2000-02-01), Wang et al.
patent: 6037248 (2000-03-01), Ahn
patent: 6043167 (2000-03-01), Lee et al.
patent: 6051073 (2000-04-01), Chu et al.
patent: 6051477 (2000-04-01), Nam
patent: 6066574 (2000-05-01), You et al.
patent: 6107192 (2000-08-01), Subrahmanyan et al.
patent: 6114259 (2000-09-01), Sukharev et al.
patent: 6147012 (2000-11-01), Sukharev et al.
patent: 6153524 (2000-11-01), Henley et al.
patent: 6204192 (2001-03-01), Zhao et al.
patent: 6232658 (2001-05-01), Catabay et al.
patent: 198 04 375 (1999-07-01), None
patent: 0 706 216 (1996-04-01), None
patent: 0 949 663 (1999-10-01), None
patent: 63-003437 (1988-01-01), None
patent: 2000-267128 (2000-09-01), None
patent: WO 99/41423 (1999-08-01), None
Chu, Paul K., et al., “A New Way to Make SOI Wafers”,Solid State Technology, May, 1997.
Dobson, C.D., et al., “Advanced SiO2Planarization Using Silane and H2O2”,Semiconductor International, Dec. 1994, pp 85-88.
En, William G., et al., “The Genesis Process™:
Gurley Lynne A.
LSI Logic Corporation
Niebling John A.
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