Metal fusion bonding – Process – Plural joints
Reexamination Certificate
1997-03-13
2001-12-18
Elve, M. Alexandra (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S246000, C257S737000, C257S738000, C438S613000, C438S614000
Reexamination Certificate
active
06330967
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a process and structure for adhering a material to a supporting substrate. In particular, the present invention describes a fabrication process and structure for attaching a chip or other substrate having a ball grid array to a chip carrier or printed circuit board.
BACKGROUND OF THE INVENTION
An electronic circuit contains many individual electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form circuits, and the circuits are interconnected to form functional units. Microelectronic packages, such as chips, modules, circuit cards, circuit boards, and combinations thereof, are used to protect, house, cool, and interconnect circuit components and circuits.
Within a single integrated circuit (IC), circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an integrated circuit chip. The chip that is enclosed within its module is referred to as the first level of packaging.
There is at least one further level of packaging. The second level of packaging is a circuit card. A circuit card performs at least four functions. First, the circuit card is used if the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip. Second, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Third, the circuit card provides for signal interconnection with other circuit elements. Fourth, the second level package provides for thermal management, i.e., heat dissipation.
The industry has moved away from the use of pins as connectors for electronic packaging due to the high cost of fabrication, the unacceptable percentage of failed connections which require rework, the limitations on input/output (I/O) density, and the electrical limitations of the relatively high resistance connectors. Solder balls are superior to pins in all of the above features as well as being surface mountable, which has obvious implications given the increasingly small dimensions in the forefront technologies today.
Solder mounting is not a new technology. The need remains to improve the solder systems and configurations, however, in electronic structures. The use of solder ball connectors has been applied to the mounting of integrated circuit chips using the so-called “flip-chip” or controlled collapse chip connection (C
4
) technology. Many solder structures have been proposed to mount integrated circuit chips, as well as to interconnect other levels of circuitry and associated electronic packaging.
The basic structure is that of a minute solder portion, generally a ball, connected to a bonding site on one of the parts to be electrically joined. The assembly of the part, bonding pad, and solder is then brought into contact with a solderable pad on a second part and the solder is reflowed to achieve the connection. One of the major drawbacks of this configuration is that the solder balls do not always remain in place before connection, during processing, or upon rework. During rework, not only the solderable pad, but also the solder itself, becomes molten. There is no guarantee, therefore, that the solder will remain associated with the first part during heating in subsequent processing.
To handle a large number of I/O's per chip, various “flip chip” bonding methods have been developed. In these so-called “flip chip” bonding methods, the face of the IC chip is bonded to the card.
Flip chip bonding allows the formation of a pattern of solder bumps on the entire face of the chip. In this way, the use of a flip chip package allows full population area arrays of I/O. In the flip chip process, solder bumps are deposited on solder wettable terminals on the chip and matching footprints of solder wettable is terminals are provided on the card. The chip is then turned upside down, hence the name “flip chip,” the solder bumps on the chip are aligned with the footprints on the substrate, and the chip-to-card joints are all made simultaneously by the reflow of the solder bumps.
The wettable surface contacts on the card are the “footprint” mirror images of the solder balls on the chip I/O's. The footprints are both electrically conductive and solder wettable. The solder wettable surface contacts forming the footprints are formed by either thick film or thin film technology. Solder flow is restricted by the formation of dams around the contacts. The chip is aligned, for example self-aligned, with the card, and then joined to the card by thermal reflow. The assembly of chip and card is then subject to thermal reflow in order to join the chip to the card.
When the packaging process uses organic carriers (e.g., laminates, teflon, and flex), the first level flip chip attach process must be performed at low temperature. Although it would seem that a low temperature flip chip would be desirable, this is not the case because the first level interconnection would reflow during subsequent second level attach (assuming a laminate chip carrier). It is well known that the amount of molten solder in this type of flip chip interconnection can cause reliability problems, such as severe delamination.
A representation of the general arrangement of an unassembled package
1
is shown in FIG.
1
. This package
1
includes an IC chip
10
and a card
21
to be joined by C
4
bonding. Solder bumps
30
are present on the I/O leads
11
of the IC chip
10
. The solder bumps
30
on the IC chip
10
correspond to recessed lands
151
on the circuit card
21
.
A cutaway view of the assembled microelectronic circuit package
1
is shown in FIG.
2
.
FIG. 2
shows an IC chip
10
mounted on a circuit card
21
. The IC chip
10
is electrically connected and metallurgically bonded to the circuit card
21
by the solder joints
32
.
FIG. 2
also shows the internal circuitry of the card
21
, for example through holes and vias
23
, and signal planes and power planes
25
.
FIG. 3
is a cutaway view of an IC chip
10
and card
21
with a reflowed solder ball connector
31
. This structure is representative of the prior art. The IC chip
10
has an array of I/O leads
11
, i.e., contacts
12
on the internal leads
13
. The individual contacts
12
are surrounded by a passivation layer
14
. Recessed within the passivation layer
14
is the ball limiting metallurgy (BLM) which comprises, for example, metallization layers of chromium (Cr) and copper (Cu)
15
, and a flash layer
16
, e.g., a gold (Au) flash layer
16
. Extending outwardly from the chip
10
is the solder ball
30
. The solder ball
30
has a characteristic spherical shape because it has been reflowed. The circuit card
21
has a eutectic lead/tin (Pb/Sn) coated in land
151
.
Although the art of semiconductor chip to supporting substrate connections and packaging is well developed, there remain problems inherent in this technology, as described above. Therefore, a need exists for a process and structure for increasing the reliability and decreasing the complexity of fabrication of the connection between an area array package and a supporting substrate.
SUMMARY OF THE INVENTION
The present invention provides a process and structure for increasing the reliability of the connection between an area array package and a supporting substrate by providing a thin layer of Sn on the end of a Pb-rich ball, reflowing to form a eutectic interconnection, and annealing to diffuse the Sn into the Pb.
According to one aspect of the present invention, a ball comprising Pb is deposited on solder wettable input/output (I/O) terminals of an IC chip; a layer of Sn having a thickness of preferably less than 10.2
Milewski Joseph M.
Woychik Charles G.
Elve M. Alexandra
Fraley, Esq. Lawrence R.
International Business Machines - Corporation
Ratner & Prestia
Stoner Kiley
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