Process to personalize master slice wafers and fabricate high de

Details Process to personalize master slice wafers and fabricate high de Process to personalize master slice wafers and fabricate high de

1996-10-10

1999-01-12

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

438599, H01L 2170

Patent

active

058588175

ABSTRACT:
A method of making gate array ASIC components from a master slice wafer having a first conducting layer containing logic elements, a second conducting layer containing first electrically conducting elements extending in a first direction, and a third conducting layer comprises interconnecting at least some of the logic elements to one another with a single masking process step by defining, on the third conducting layer, second conducting elements connected to the first electrically conducting elements to define connections between the logic elements.

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