Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-02-07
2001-10-02
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S156000, C438S250000, C438S253000, C257S067000, C257S329000
Reexamination Certificate
active
06297132
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to control the doping profile of the channel region, in a lateral direction, formed via ion implantation procedures, in the channel region of a metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
The continuing objective of increasing device density, and increasing device performance, via micro-miniaturization, or via the use of sub-micron features for MOSFET devices, has led the semiconductor devices has directed the semiconductor industry to the fabrication of MOSFET device with channel lengths as narrow as 0.18 um, Although the use of MOSFET devices, featuring narrow channel lengths, have satisfied the density and performance objectives of the semiconductor industry, formation of specific regions of the sub-micron MOSFET devices, such lightly doped source/drain, (LDD), regions, as well as an anti-punchthrough region, located in the channel region of the MOSFET device, have become more difficult to achieve and control For example the ion implantation, used to form the LDD, or source/drain extensions, can result in encroaching, sphere-like profiles, sometimes decreasing the designed channel length, or effective channel length, (Leff), to an undesirable length of less than 0.18 um. In addition, subsequent high temperature processing steps, can result in lateral diffusion of the LDD regions, again resulting in an undesirable shortening of the channel length. For these reasons a lateral delta doping region, or an anti-punchthrough region, is placed in the channel region, between LDD regions to insure the integrity of the dimension of the channel length, as well as to minimize jointing, or touching of the depletion regions created at the junction of the LDD regions, and the semiconductor substrate.
This invention will describe a process for forming a lateral delta doping region, which has the added advantage of serving as an anti-punchthrough region, between LDD regions. However this invention will feature an anti-punchthrough region that will consume less lateral space in the channel region, than counterpart anti-punchthrough regions, fabricating without the use of this invention, thus still reducing the LDD jointing phenomena, however also reducing the capacitance generated with larger area, anti-punchthrough regions. The smaller area, or truncated, anti-punchthrough region, is formed via a novel process sequence, featuring the formation of spacers, on the sides of a trench shape, which will subsequently be used to accommodate a polysilicon gate structure, followed by the anti-punchthrough ion implantation procedure, placing the lateral delta doping region in an area of the subsequent channel region, reduced in lateral dimension by the presence of the spacers. Prior art, such as Lee et al, in U.S. Pat. No. 5,856,225, shows a anti-punchthrough region formed in a trench, with the trench next filled with a polysilicon gate structure. In that prior art however the critical gate insulator layer, as well as the critical sidewall spacers, are subjected to the removal of the dummy gate structure, and thus used as part of the final gate structure. In contrast this invention does not feature the use of a dummy gate structure, and therefore the gate insulator layer, and sidewall spacers, are not formed prior to the anti-punchthrough region, and therefore are not subjected to the processes used to form and to remove, the insulator shape, which in turn is used to provide the trench needed for definition of the MOSFET polysilicon gate structure.
SUMMARY OF THE INVENTION
It is an object of this invention to form a lateral delta doping profile, or a narrow, antipunchthrough region, in a portion of the channel region, of the MOSFET device.
It is another object of this invention to form a first opening in an insulator layer, overlying the subsequent channel region, in a semiconductor substrate, then form spacers on the sides of the first opening in the insulator layer, to create a narrower, second opening in the insulator layer.
It is yet another object of this invention to form the anti-punchthrough region, in a portion of the semiconductor substrate, using the second opening in the insulator layer, as a mask.
It is still yet another object of this invention to form a polysilicon gate structure in the first opening in the insulator layer.
In accordance with the present invention a process for forming a narrow, anti-punchthrough region, laterally located in the center of a subsequent channel region of a MOSFET device, via an ion implantation procedure performed through an opening in an insulator layer, which has been narrowed via use of inside spacers, located on the sides of an opening in the insulator layer, is described. A first opening is made in a silicon nitride-silicon oxide, composite insulator layer, exposing the portion of a semiconductor substrate to be used for a MOSFET channel region. After formation of a threshold voltage adjust, ion implantation procedure, in a region of the semiconductor substrate, not covered by the composite insulator layer, or into the region of the semiconductor substrate exposed in the first opening in the composite insulator layer, polysilicon, or polysilicon-silicon oxide, first spacers, are formed on the sides of the first opening, creating a second opening, reduced in width by the addition of the first spacers on the sides of the first opening in the composite insulator layer. A lateral delta doping, or an antipunchthrough region, is then formed via an ion implantation procedure, in a region of the semiconductor substrate not covered by the composite insulator layer, or by the first spacers. After selective removal of the first spacers, a gate insulator layer is grown on the region of the semiconductor substrate exposed in the first opening. A polysilicon layer is next deposited, than subjected to a chemical mechanical polishing procedure, creating a polysilicon gate structure, in the first opening, in the composite insulator layer. After selective removal of the composite insulator layer, lightly doped source/drain regions are formed in a region of the semiconductor substrate, not covered by the polysilicon gate structure. This is followed by the formation of second spacers, on the sides of the polysilicon gate structure, and the formation of heavily doped source/drain regions, in a region of the semiconductor substrate, not covered by the polysilicon gate structure, or by the second spacers.
REFERENCES:
patent: 5283455 (1994-02-01), Inoue et al.
patent: 5334862 (1994-08-01), Manning et al.
patent: 5472897 (1995-12-01), Hsu et al.
patent: 5600168 (1997-02-01), Lee
patent: 5686321 (1997-11-01), Ko et al.
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5879998 (1999-03-01), Krivokapic
patent: 5937297 (1999-08-01), Peidous
Chu Shao-Fu Sanford
Shao Kai
Zhang Jiong
Chartered Semiconductor Manufacturing Ltd.
Elms Richard
Luu Pho
Pike Rosemary L. S.
Saile George O.
LandOfFree
Process to control the lateral doping profile of an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process to control the lateral doping profile of an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to control the lateral doping profile of an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2568036