Process to control semiconductor wafer yield

Details Process to control semiconductor wafer yield Process to control semiconductor wafer yield

2006-08-15

2009-10-13

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257SE29109, C257SE21359, C438S270000

Reexamination Certificate

active

07602015

ABSTRACT:
The size of BVDSSdistribution is controlled by the active manipulation of the distribution of silicon parameters across a wafer to offset opposing effects inherent in the wafer fabrication process. Thus, the resistivity of the silicon wafer is increased toward the edge of the wafer. This offsets the drop-off of BVDSSacross the wafer caused in wafer fabrication by deeper trenches at the edge of the wafer. This causes a flatter BVDSSprofile across the wafer and significantly reduced BV distribution over the wafer.

REFERENCES:
patent: 6129047 (2000-10-01), Nakamura
patent: 6639301 (2003-10-01), Andoh
patent: 2002/0121663 (2002-09-01), Azam et al.
patent: 2003/0034511 (2003-02-01), Hurley et al.
patent: 2004/0077149 (2004-04-01), Renau
patent: 2004/0262677 (2004-12-01), Harada
patent: 2005/0001240 (2005-01-01), Choi et al.
patent: 2005/0124085 (2005-06-01), Andoh et al.

Affiliated with

Also associated with

Rating

Process to control semiconductor wafer yield does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process to control semiconductor wafer yield, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to control semiconductor wafer yield will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4064536