Process sequence to improve DRAM data retention

Details Process sequence to improve DRAM data retention Process sequence to improve DRAM data retention

1998-11-20

2001-08-14

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S705000

Reexamination Certificate

active

06274481

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and more particularly to improving data retention in DRAM devices.
BACKGROUND
Dram Processes
In current DRAM process, three factors have been identified as degrading the cell data retention. Since the length of time between refreshes of the memory, also known as the “pause”, is a very important parameter in DRAM, resolving these factors is a high priority.
First, the surface of the silicon can be damaged by plasma induced chemical damage during the contact etch process. This plasma induced damage includes damage caused by bombardment of the surface with highly energetic fluorine ions, as well as the presence of oxygen ions, which are formed during the etch of the BPSG.
Secondly, the silicon can be contaminated by impurities in the BPSG layer being etched or by carbon from the etch itself. These impurities can diffuse into the silicon, and they can be lifetime killers for the circuits.
A third factor which affects the data retention is the electric field surrounding the contact regions. A contact diffusion which has greater straggle, i.e., is more scattered, has a lower electric field. This lower electric field is desirable, since it has effect on the data retention.
Innovative Structures and Methods
The present application discloses that the sidewall nitride etch is stopped short, so that a thin layer (e.g. 10-30 nm) of nitride is left on the silicon surface of the active areas. The nitride will be patterned and etched so that the thinned layer of nitride remains in the DRAM array, but only nitride sidewall spacers are left in the peripheral logic areas. The remaining thin layer of nitride protects the silicon under the contact area in the DRAM during the subsequent etch, while its presence in the logic transistors would adversely affect performance.
When contacts are etched for the DRAM cells, a two-step process is used. First, a highly selective etch is performed to ensure there is no damage to the first gate nitride. After reaching the thin nitride layer, the etch process is stopped while dopants for the contact are implanted through tie nitride layer. Then the etch process is resumed with an appropriate chemistry to etch through the nitride layer.
The presence of the nitride layer during the contact etch and DRAM implantation has a very positive affect, reducing both damage and contamination to the silicon. Additionally, implanting the contact through the nitride layer causes the dopant to be more scattered, which improves the electric field. This process has been tested in a 0.2 micron layout, as discussed below.
Advantages of the disclosed methods and structures include:
silicon damage during etch is reduced or eliminated;
silicon contamination during etch is reduced or eliminated;
electric field at contact is improved;
data retention problems are reduced or eliminated;
reliability of DRAM array is increased;
no increase in cell height;
can be done with as little as one additional step in flow.


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