Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-08
2004-08-10
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S633000, C438S637000, C438S685000
Reexamination Certificate
active
06774039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and processing, and in particular, to electroplating and fabrication of layers prior to electroplating.
2. Discussion of the Related Art
Integrated circuits fabricated on semiconductor substrates for very and ultra large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next.
As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers needs to be as small as possible. One way to reduce the size of interconnection lines and vias is to use copper (Cu) as the interconnect material instead of conventionally used materials such as aluminum (Al). Because copper has lower resistivities and significantly higher electromigration resistance as compared to aluminum, copper advantageously enables higher current densities experienced at high levels of integration and increased device speed at higher frequencies. Thus, major integrated circuit manufacturers are transitioning from aluminum-based metallization technology to dual damascene copper technology.
However, the use of copper as the interconnect material presents various problems. For example, there is currently no production-worthy dry etch process for Cu. This necessitates the use of a dual damascene “inlaid” approach. In the dual damascene approach, a dielectric or insulating diffusion barrier layer is deposited over a copper layer. The dielectric layer is then patterned, e.g., by conventional masking and etching techniques, to form a two-step connection having a narrower lower portion (or via portion) exposing desired connection areas on the underlying patterned metal layer and a wider upper portion (or trench portion) that will form the next layer of metal lines. Copper is then deposited to fill the via and trench, such as by electroplating. Excess copper is then removed, e.g., by a chemical mechanical polish (CMP) process. The resulting structure is a via (the filled via portion) connecting the desired areas in the underlying metal layer with an overlying copper line (the filled trench portion).
One of the consequences of using copper is that copper atoms can readily diffuse into adjacent ILD or other dielectric layers, which can compromise their integrity as insulators or cause voids in the conductors because of out-diffusion of the copper. As a result, a diffusion barrier layer is typically formed over the trenches and vias prior to forming the copper layer. Materials for the barrier layer include Tantalum (Ta), Tungsten Nitride (WN), Titanium Nitride (TiN), Tantalum Nitride (TaN), Silicon Nitride (SiN), and Tungsten (W). The barrier layer may be conformally deposited using a conventional chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process or other known deposition process.
This technique relies on electroplating to fill small features (of order 100 nm in width) with copper. In order for this to work, a “seed layer” must be applied to the wafer to provide enough electrical conductance across the wafer, so that a sufficiently uniform layer can be electroplated. In order to electroplate copper, the underlying surface has to be able to conduct current across its surface since electroplating is an electrochemical process. The diffusion barrier typically has high sheet resistivity. Because current must flow through this layer to reach the center portions of the wafer, the voltage drop between the wafer center and its edge may be excessive. Thus, a highly conductive seed layer, typically copper, is deposited over the diffusion barrier. Deposition can be performed by any suitable process, such as PVD.
A key property of the seed layer is that it should have a low sheet resistance per square. Processes in the field at present require less than 1 ohm per square seed resistance, although with improvements in electroplating technology, films as resistive as 5 ohms per square may eventually be suitable seeds. The approximate thickness of films needed to achieve this sheet resistance is shown for various metals in Table 1 below.
TABLE 1
Thick-
ness
Thickness
Thickness
for
for
for
20
Metal
5 ohm/sq
10 ohm/sq
ohm/sq
Cu (2 &mgr;&OHgr;cm)
4
nm
2
nm
1
nm
W (CVD) (16 &mgr;&OHgr;cm)
32
nm
16
nm
8
nm
Co (CVD) (11 &mgr;&OHgr;cm)
22
nm
11
nm
5.5
nm
TiN (ALD) (170 &mgr;&OHgr;cm)
340
nm
170
nm
85
nm
These calculations are based on the bulk conductivity of the metals listed. In practice, a larger thickness is needed. The thin film material used does not achieve bulk conductivity, and electron scattering effects also decrease the effective conductivity of such thin films. One problem with depositing a thin copper seed layer is that they do not generally coat the barrier layer in a uniform manner. Rather, voids or non-continuous seed layer regions on the sidewalls are often present, thereby resulting in the inability to properly apply a subsequent electrochemically deposited copper layer. When a discontinuity is present in the seed layer, the portion of the seed layer that is not electrically connected to the bias power supply does not receive deposition during the electroplating process. This is particularly prevalent with high aspect ratio, sub-micron features, where the bottom surface of these features are especially difficult to fill using PVD.
Further, thin seed layers tend to include spikes that impact the uniformity of the subsequent electrolytically deposited metal layer. Such spikes result in high potential regions at which the copper deposits at a higher rate than at other, more level regions. During the electroplating, the voltage and current near the perimeter of the wafer tends to be substantially higher than the voltage and current near the central portions of the wafer. Consequently, copper plates onto the surface of the wafer much more rapidly towards the edges of the wafer, resulting in thicker copper layers towards the perimeter of the wafer. A thicker seed layer can offset this characteristic. Moreover, as shown by Broadbent et al., J. Vac. Sci. Technol., B 17(6), p. 2584 (1999), which is incorporated by reference, the features etched into the dielectric that are coated with the seed layer increase the effective sheet resistance, so that a still thicker seed layer is called for.
However, there is a limit to the combined barrier and seed layer thickness that can be deposited inside features while still allowing for filling of the feature by electroplating. The limit arises because there is a maximum aspect ratio of a feature that can be successfully filled by electroplating. Until now, PVD has been used to deposit the seed layers. As shown in
FIG. 1A
, PVD forms a seed layer
10
having a much thicker layer on the planar surface (“field”) of the wafer than within the small features such as vias
20
and trenches. The thicker material in the field allows current to be conducted across the wafer, while there is sufficient copper in the features to allow electroplating in the features. With lower aspect ratio features, e.g., <3:1, the opening of feature stays open long enough to allow a void-free fill with the electroplating.
But successive reduction in feature sizes has meant that there is increasing difficulty in this process. When the seed layer is formed on the sidewalls as well as the bottom of the feature, the electroplating process deposits the metal on both surfaces within the feature.
FIG. 1A
shows the opening of the feature being “closed off” with seed layer deposition by PVD. With higher aspect ratio features, the electroplated metal growth on the wall tends to clos
Chen Jack
Chen Tom
MacPherson Kwok & Chen & Heid LLP
Nguyen Thanh
Novellus Systems Inc.
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