Process of vertically stacking multiple wafers supporting...

Details Process of vertically stacking multiple wafers supporting... Process of vertically stacking multiple wafers supporting...

2007-01-02

2007-01-02

Graybill, David E. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

C257S686000, C257S777000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE23085, C257SE21614

Reexamination Certificate

active

10855032

ABSTRACT:
A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

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