Process of manufacturing semiconductor device

Details Process of manufacturing semiconductor device Process of manufacturing semiconductor device

2002-02-05

2004-09-21

Pham, (Vikki) Long (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S645000

Reexamination Certificate

active

06794267

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2001-46197 filed on Feb. 22, 2001, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process of manufacturing a semiconductor device. More particularly, it relates to a process for solving a problem in that the polish rate (=polished amount/unit time) of an interlayer insulating film during chemical mechanical polishing is extremely high in a wafer periphery portion.
2. Description of Related Art
In accordance with integration at higher level and increase in capacity of integrated circuit devices, a wiring structure of semiconductor devices is getting to be miniaturized and multilayered. Accordingly, a process of forming an interwire insulating film or an interwire plug of greater flatness has been demanded. For obtaining such an interwire insulating film or an interwire plug of greater flatness, widely employed is a process of flattening an interlayer insulating film by chemical mechanical polishing (hereinafter abbreviated as CMP), forming connection holes by photolithography and dry etching, depositing metal such as tungsten to fill the connection holes and removing the metal on the interlayer insulating film by CMP.
It is generally known that a film to be polished, such as an interlayer insulating film or the like, is deposited at the deposition amount varying over the wafer surface.
FIG. 4
shows the variation of the deposition amount among portions of the wafer surface, wherein A is a center portion, C is an edge portion and B is an intermediate portion between A and C. Type
1
shows a film deposited at the deposition amount decreasing from A to C, type
2
shows a film deposited at the deposition amount decreasing from A to B and increasing from B to C, type
3
shows a film deposited at the deposition amount increasing from A to C, and type
4
shows a film deposited at the deposition amount increasing from A to B and decreasing from B to C. The variation in deposition amount depends on the deposition rate.
As shown in
FIG. 3
, in the CMP step, a wafer periphery portion of about 1-2 mm width from a wafer edge is polished at the polish rate twice or more as great as that of a central portion ranging from a point of about 3 mm from the wafer edge to a wafer center. Accordingly, in polishing the film deposited at the deposition amount of type
1
or
4
shown in
FIG. 4
, there is a problem in that the film may excessively be polished at the wafer periphery portion.
FIGS.
6
(
a
) to
6
(
d
) are sections illustrating the steps of manufacturing a conventional semiconductor device. Referring to FIG.
6
(
a
), a first insulating film
103
made of a BPSG film is formed by chemical vapor deposition (CVD) on a substrate
101
on which desired semiconductor devices are formed and the surface of the first insulating film is flattened by CMP. A lower wiring layer
104
is then formed on the first insulating film
103
and a second interlayer insulating film
105
made of a TEOS film is deposited thereon by CVD.
The first insulating film
103
is deposited at the deposition amount of type
2
or
3
mentioned above and is almost flattened by the following CMP.
The second interlayer insulating film
105
is deposited at the deposition amount of type
1
or
4
. A thickness of the second interlayer insulating film
105
at a wafer edge
109
is smaller than that of the other portion.
Then, the second interlayer insulating film
105
is flattened by CMP as shown in FIG.
6
(
b
).
Photolithography and dry etching are carried out to form a connection hole
106
and a conductive film
107
such as a tungsten film is deposited on the entire surface of the wafer by CVD as shown in FIG.
6
(
c
). Before depositing the conductive film
107
, a TiN/Ti layer (not shown) is formed by sputtering for improving the adhesion to the underlying layer.
Then, as shown in FIG.
6
(
d
), the conductive film
107
on the second interlayer insulating film
105
is removed by CMP while leaving the conductive film
107
only in the connection hole
106
, thereby forming a plug
108
.
According to the process, the second interlayer insulating film
105
in the neighborhood of the wafer edge
109
is polished at an extremely high polish rate during CMP, thereby the thickness of the second interlayer insulating film
105
in the neighborhood of the wafer edge
109
is reduced as shown in FIG.
6
(
b
).
On the other hand, FIGS.
7
(
a
) and
7
(
b
) show the steps of manufacturing another conventional semiconductor device. As shown in FIG.
7
(
a
), a first interlayer insulating film
114
is deposited by CVD on a substrate
113
on which desired semiconductor devices are formed and then flattened by CMP. The first interlayer insulating film
114
is deposited at the deposition amount of type
1
or
4
shown in FIG.
4
and thus its thickness in the neighborhood of a wafer edge
115
is small.
Then, as shown in FIG.
7
(
b
), the first interlayer insulating film
114
is flattened by CMP before forming a wiring layer.
According to the process, the first interlayer insulating film
114
has a small thickness in the neighborhood of the wafer edge
115
as shown in FIG.
7
(
a
). Since the CMP is carried out at the polish rate extremely high in a wafer periphery portion of about 1-3 mm width from the wafer edge as shown in
FIG. 2
, the substrate
115
in the neighborhood of the wafer edge is also polished, which is not preferable.
As a solution for the extremely high polish rate in the neighborhood of the wafer edge, for example, Japanese Unexamined Patent Publication No. Hei 9 (1997)-139366 describes a technique for providing a retainer ring, a part of a wafer retaining member, with a rounded section at its circumference or an adjusted height to prevent extreme polishing in the wafer periphery portion, thereby maintaining an appropriate polish rate to obtain a flat surface.
However, even by the above technique, secondary deformation
122
in a polish cloth
121
contacting the neighborhood of a wafer edge
120
as shown in
FIG. 8
is unavoidable, which causes a repulsion force
123
to the neighborhood of the wafer edge
120
. Thus, it is impossible to inhibit the extremely high polish rate in the neighborhood of the wafer edge
120
. In
FIG. 8
, reference numeral
124
denotes the retainer ring,
125
a wafer and
126
an insert pad.
In the step of forming the interwire plugs, the conductive film
107
is deposited on the second interlayer insulating film
105
as shown in FIG.
6
(
c
) and then removed by CMP. However, since the second interlayer insulating film
105
has been polished at an extremely high polish rate in a wafer periphery portion
110
, the conductive film
107
is not completely removed from the wafer periphery portion
110
and remains there as indicated by a reference numeral
111
. Thus, an undesired object is left on the wafer.
On the other hand, in the step of forming the interlayer insulating film on a transistor, the substrate
113
itself is also polished during the flattening of the first interlayer insulating film
114
as shown in FIG.
7
(
b
), which may generate an undesired object on the wafer.
SUMMARY OF THE INVENTION
In view of the above circumstances, the present invention provides a process of manufacturing a semiconductor device capable of preventing the generation of the undesired object after CMP.
According to the present invention, provided is a process of manufacturing a semiconductor device comprising the step of chemical mechanical polishing for flattening an interlayer insulating film deposited on a wafer on which desired elements are in advance formed, wherein a stopper layer is formed on a region which will be excessively polished through the chemical mechanical polishing before or after forming the interlayer insulating film.
According to the process of the present invention, the stopper layer is provide

Affiliated with

Also associated with

Rating

Process of manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of manufacturing semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3241337