Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-29
2003-11-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06642138
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to inter-level isolation of interconnects in semiconductor devices and more particularly to integration processes for producing very low-k isolation of copper interconnects.
Copper interconnects are formed using a dual damascene process. The incorporation of low-k insulator material may be accomplished by depositing a first layer of low-k dielectric material over a copper interconnect. This may be followed by an optional etch stop barrier insulator and then a second layer of low-k material. A via is then etched through the second layer of low-k material, any etch stop barrier insulator, and the first layer of low-k dielectric material to reach the copper interconnect. A trench is then etched into the second layer of low-k material to aid in forming another layer of copper interconnects. Barrier metal and copper are deposited by sputtering, chemical vapor deposition (CVD), electrochemical deposition, or a combination of these methods. The deposited copper, and possibly the barrier metal, will then be planarized using chemical mechanical polishing (CMP) to form copper interconnects.
Air gaps have been used for intra-level insulators for copper, while using silicon oxide at the inter-level copper layers. The air gaps are formed by decomposing Unity™ sacrificial polymer. However, copper is in direct contact with oxide, which may result in copper diffusion into the oxide causing leakage current flow between adjacent copper lines.
SUMMARY OF THE INVENTION
Accordingly, a method of fabricating copper interconnects to integrate air gaps as inter-level insulator or intra-level and inter-level insulators is provided. A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing. One possible candidate for use as a sacrificial polymer is a copolymer of butylnorbornene and triethoxysilyl norbornene dissolved as a 6-12 wt % solution in mesitylene.
A double hard mask, which comprises a first hard mask and a second hard mask, may be used to pattern the sacrificial polymer. The first hard mask may be a metal film, such as AlCu, Ti, Ta, TiN or TaN. The second hard mask may be silicon dioxide.
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Article entitled, “NURA: A Feasible, Gas Dielectric Interconnect Process”, by M. B. Anand et al., published in VLSI Symposium, Technical Digest, pp. 82-83, 1996.
Article entitled, “Use of Gas as Low-k Interlayer Dielectric in LSI's: Demonstration of Feasibility”, M. B. Anand et al., published in IEEE ED-44, #11, pp. 1965-1971, 1997.
Article entitled, “Air-Gaps in 0.3 &mgr;m Electrical Interconnections” by Paul A. Kohl et al., published in IEEE EDL-21, pp 557-559, 2000.
Manufacture's datasheet entitled, “Unity Sacrificial Polymer—Processing Overview”, by BFGoodrich, 6 pages.
Hsu Sheng Teng
Pan Wei
Hoang Quoc
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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