Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-11-06
1998-06-30
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438702, 438700, H01L 2188, H01L 2194
Patent
active
057733619
ABSTRACT:
A microcavity structure and a method for forming an integrated circuit device including a microcavity structure is disclosed. This invention includes a layer or substrate having a topography such as a pair of raised features. A void forming material, such as a Boro-Phosphorus Silicate Glass (BPSG) is deposited on the substrate such that a void is formed therein. A pinning material having a relatively greater density than the void forming material is deposited over the void forming material. The materials are then annealed by a process such as Rapid Thermal Anneal (RTA). The materials are then polished, by for example, Chemical Mechanical Polishing (CMP) to expose the top of the void. The void is then etched using an anisotropic etch, such as Reactive Ion Etch (RIE) to remove the void forming material. The method may be used to provide self-aligned contact vias.
REFERENCES:
patent: 4474831 (1984-10-01), Downey
patent: 4781945 (1988-11-01), Nishimura et al.
patent: 4835597 (1989-05-01), Okuyama et al.
patent: 4962063 (1990-10-01), Maydan et al.
patent: 5004704 (1991-04-01), Maeda et al.
patent: 5094984 (1992-03-01), Liu et al.
patent: 5119164 (1992-06-01), Silwa, Jr. et al.
patent: 5188987 (1993-02-01), Ogino
patent: 5192715 (1993-03-01), Silwa, Jr. et al.
patent: 5204288 (1993-04-01), Marks et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5268333 (1993-12-01), Lee et al.
patent: 5278103 (1994-01-01), Mallon et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5444026 (1995-08-01), Kim et al.
patent: 5508234 (1996-04-01), Dusablon et al.
patent: 5518962 (1996-05-01), Murao
patent: 5641712 (1997-06-01), Grivna et al.
Wolf, Stanley Silicon Processing For The VLSI Era, vol. 2, p. 333 (1990).
Cronin John Edward
Stamper Anthony Kendall
Bowers Jr. Charles L.
Chadurjian Mark F.
International Business Machines - Corporation
Whipple Matthew
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