Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-10
2001-02-06
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S672000, C427S294000, C427S123000, C427S398100, C427S383100
Reexamination Certificate
active
06184131
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a thin film forming technology used in fabrication of a semiconductor device and, more particularly, to a process of forming a solid thin film from a layer of liquid material and a film forming apparatus used therein.
DESCRIPTION OF THE RELATED ART
A circuit component of a semiconductor integrated circuit device had been miniaturized, and the cross section of each component layer before the miniaturization was similar to the cross section of a corresponding layer after the miniaturization. If a manufacture reduces the width and the height of a conductive layer at a certain ratio, the current density is drastically increased, and the large current density damages the conductive layer. In order to improve the durability of the conductive layer, the manufacture reduces the width at a large reduction ratio and the height at a small reduction ratio, and such anisotropic reduction increases the circuit components without sacrifice of the durability. However, the anisotropic reduction enlarges the aspect ratio of a contact hole formed in the conductive layer, and the contact hole is imperfectly plugged with conductive material. Various planarization technologies have been proposed for improving step coverage.
One of the prior art planarization technologies is disclosed in Japanese Patent Publication of Unexamined Application No. 4-99030, and the prior art process is illustrated in
FIGS. 1A
to
1
D. A silicon substrate
1
is overlain by an insulating layer
2
, and a first-level aluminum wiring
3
is patterned on the insulating layer
2
. The first-level aluminum wiring
3
and the exposed area of the insulating layer
2
are covered with an inter-level insulating layer
4
, and a contact hole
4
a
is formed in the inter-level insulating layer
4
in such a manner as to expose the first-level aluminum wiring
3
thereto as shown in FIG.
1
A.
Subsequently, metal is deposited over the entire surface of the resultant semiconductor structure shown in
FIG. 1A
, and forms a metal layer
5
. The metal can not achieve good step coverage, and a recess
5
a
takes place in the metal layer
5
as shown in FIG.
1
B.
Subsequently, metal-containing liquid is prepared. Powder of chromium and tin is mixed into volatile solvent in methyl system or isopropyl system. The metal-containing liquid is dropped onto the metal layer
5
in the atmospheric ambience, and the metal-containing liquid is spread over the metal layer
5
. The volatile solvent is removed at 300 degrees to 400 degrees in centigrade, and the metal powder forms a low fusing point metal layer
6
. The low fusing point metal layer
6
buries the recess
5
a,
and creates a smooth top surface
6
a
as shown in FIG.
1
C.
The low fusing point metal layer
6
is uniformly etched away without an etching mask, and the metal layer
5
is exposed, again. A piece
6
b
of low fusing point metal is left in the recess
5
a,
and the metal layer
5
is patterned into a second-level metal wiring
5
b
as shown in FIG.
1
D.
Another prior art planarization technology is disclosed by Y. Shacham-Diamand et al in “ULSI Application of Spin-On Titanium-Nitride”, Advanced Metallization for ULSI Applications, Oct. 28-30, 1991, pages 43 to 45, and
FIGS. 2A
to
2
C illustrate the prior art smoothening technology disclosed therein.
Firstly, a silicon substrate
10
is prepared, and the major surface of the silicon substrate
10
is covered with an insulating layer
11
. The insulating layer
11
is partially removed, and a hole
11
a
is formed in the insulating layer
11
. The silicon substrate
10
is exposed to the hole
11
a
as shown in FIG.
2
A.
Subsequently, colloidal liquid
12
a
is dropped onto the resultant structure in the atmospheric ambience, and is spread over the entire surface as shown in FIG.
2
B. The colloidal liquid
12
a
is treated with heat at 450 degrees in centigrade in vacuum, hydrogen ambience or NH
3
. Then, a titanium nitride layer
12
b
is produced from the colloidal liquid.
A problem is encountered in the prior art processes in that a void takes place in the hole
5
a
/
11
a.
Another problem is high resistivity of the order of hundreds micro-ohm cm which is two figures larger than the resistivity of aluminum.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a process of forming a thin film without a void left in a recess.
It is also an important object of the present invention to provide a firm forming apparatus used in the process for forming a thin film without a void in a recess.
To accomplish the object, the present invention proposes to force a layer of liquid material into a recess or hole.
In accordance with one aspect of the present invention, there is provided a process of forming a solid thin film, comprising the steps of: preparing a substrate structure having at least one recess open to a surface of the substrate structure; changing the temperature of the substrate structure to be lower than an ambient temperature; creating vacuum around the substrate structure; supplying liquid material onto the surface of the substrate structure so as to form a layer of liquid material on the surface; pressing the layer of liquid material so as to perfectly fill the recess with the liquid material; and heating the liquid material so as to form a solid layer from the liquid layer.
In accordance with another aspect of the present invention, there is provided a firm forming apparatus comprising a vessel defining a chamber, a holder provided in the chamber for supporting a substrate structure having a recess open to a surface of the substrate structure, a temperature controller for controlling a temperature of the substrate structure to be lower than a temperature in the chamber, a liquid material feeder supplying liquid material onto the surface for covering the surface with a layer of liquid material, a pressurizer exerting force on the layer of liquid material, and a heater heating the layer of liquid material for forming a solid layer from the layer of liquid material.
REFERENCES:
patent: 5213999 (1993-05-01), Sparks et al.
patent: 5679610 (1997-10-01), Matsuda et al.
patent: 5728626 (1998-03-01), Allman et al.
patent: 5953629 (1999-09-01), Imazeki et al.
patent: 5955140 (1999-09-01), Smith et al.
patent: 62-096325 (1987-05-01), None
patent: 1-286435 (1989-11-01), None
patent: 2-297952 (1990-12-01), None
patent: 6-310605 (1994-04-01), None
patent: 8-213390 (1996-08-01), None
patent: 9-45773 (1997-02-01), None
English Translation of Examiner's comments regarding Japanese Office Action dated Oct. 6, 1998. citing Japanese reference above.
Y. Shacham-Diamand et al.; ULSI Application of Spin-on Titanium-NitrideWaseda University The International Conference Center; Oct. 29-30, 1991; part 2-Japan Conference; pp. 43-45.
Everhart Caridad
McGuireWoods LLP
NEC Corporation
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