Process of forming recessed dielectric regions in a monocrystall

Details Process of forming recessed dielectric regions in a monocrystall Process of forming recessed dielectric regions in a monocrystall

1980-08-22

1981-12-22

Brown, J. Travis

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430317, 156647, 156649, 156657, 156662, G03C 500

Patent

active

043071805

ABSTRACT:
A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO.sub.2 layer, openings formed through the polycrystalline layer and SiO.sub.2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO.sub.2 layer.

REFERENCES:
patent: 4025411 (1977-05-01), Hom-Ma et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4104090 (1978-08-01), Pogge
patent: 4222792 (1980-09-01), Lever et al.
IBM Technical Disclosure Bulletin, vol. 21, No. 5, Oct. 1978, p. 1849.
Schaible et al., IBM Technical Disclosure Bulletin, pp. 2893-2894, vol. 17, No. 10, Mar. 1975.

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