Process of forming metal silicide interconnects

Details Process of forming metal silicide interconnects Process of forming metal silicide interconnects

1999-12-28

2001-08-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S630000, C438S649000, C438S655000, C438S660000, C438S664000, C438S682000, C438S683000

Reexamination Certificate

active

06281101

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to the formation of metal silicide interconnects, and, more particularly, to a process of forming a metal silicide interconnects using a layer of amorphous silicon.
In the manufacture of integrated circuits used in the construction of dynamic random access memories (DRAMs), static random access memories (SRAMs), and the like, interconnects are required to provide the necessary electrical paths between field effect transistors and other devices fabricated on the semiconductor substrate and the external circuitry used to pass data to and from these devices. Heavily-doped polysilicon is commonly used to form the gate as well as the drain/source contacts of a metal oxide semiconductor field effect transistor (MOSFET) because of its compatibility with the underlying silicon semiconductor structure. Titanium silicide (TiSi
2
) is commonly used in conjunction with the polysilicon to form the necessary interconnects as it is compatible with the polysilicon and, more importantly, reduces the sheet resistance of the polysilicon. Polycide contacts and interconnects comprising polysilicon and titanium silicide are increasingly being used with MOSFETs having self-aligned gates.
TiSi
2
typically exists in two phases, C49 and C54. The C49 phase of TiSi
2
occurs when a layer of TiSi
2
is first formed. The C49 phase is then annealed at a sufficient temperature to convert the higher resistivity phase C49 TiSi
2
(smaller grain size) to the lower resistivity phase C54 TiSi
2
(larger grain size). As TiSi
2
is used to lower the resistance of polysilicon, it is desirable to convert C49 TiSi
2
to C54 TiSi
2
. It is well known that the TiSi
2
salicide process is only scalable to a gate length which is larger than the C49 grain size. For gate lengths which are less than the C49 grain size, the thermal budget required to transform the C49 phase to the desired C54 phase increases dramatically, leading to agglomeration and formation of Kirkendall voids.
While agglomeration of TiSi
2
can be suppressed by high temperature sputtering of Ti, the sheet resistance (Rs) of the TiSi
2
still degrades due to Kirkendall void formation in gate lines with a width of 0.1 &mgr;m or less. The voids can be effectively suppressed by thinning the deposited Ti film as thin Ti film is easier to bend. However, thinner Ti film further degrades Rs because the silicide formation is surpassed by the nitride formation during the N
2
anneal. It is therefore desirable to enhance the silicidation process by limiting the consumption of silicon from the polysilicon during the formation of TiSi
21
while also reducing the nitridation of Ti.
Typically, TiSi
2
is formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). PVD entails sputtering titanium onto the semiconductor structure, and particularly, onto the polysilicon. TiSi
2
is then formed by annealing the structure at the appropriate temperature and for an appropriate period of time. However, the anneal consumes part of silicon in the polysilicon in forming the TiSi
2
, thereby degrading the silicidation process and increasing the formation of voids. In CVD, titanium tetrachloride (TiCl
4
) is combined with silane (SiH
4
) in the gas phase at an appropriate temperature to form TiSi
2
and HCl. However, silicon from the underlying layer of polysilicon is also partially consumed in this reaction.
A number of techniques have been devised to reduce the consumption of the underlying polysilicon in forming TiSi
2
. One such method includes pre-amorphization of the underlying polysilicon by ion implantation. However, such a method is expensive and requires complex steps in controlling the thickness and doping level of the polysilicon. Another method is disclosed in U.S. Pat. No. 5,173,450 to Wei in which a layer of polysilicon is formed over a semiconductor structure, followed by a layer of titanium and a layer of amorphous silicon. The layer of amorphous silicon is formed over the layer of titanium in order to provide a source of silicon for the formation of the TiSi
2
. However, the reaction also consumes silicon from the polysilicon with the requisite degradation of the silicidation process and increased void formation.
Accordingly, there is a need for a method of forming a metal silicide interconnect in which the silicidation process is enhanced by limiting the consumption of silicon from the polysilicon during the formation of the metal silicide and by also reducing the nitridation of the metal. Preferably, such a method could be used in forming a sub 0.1 &mgr;m gate structure, would be inexpensive, easy to implement, and would not entail excess processing steps.
SUMMARY OF THE INVENTION
The present invention meets this need by providing a method for forming a metal silicide interconnect in which a layer of metal is reacted with a layer of amorphous silicon. The amorphous silicon provides the source of silicon for the silicidation process thereby enhancing the process. The layer of amorphous silicon also reduces the nitridation of the metal.
According to a first aspect of the present invention, a process of forming an interconnect structure comprises providing at least one semiconductor layer. A layer of polysilicon is formed over the at least one semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon. A layer of metal is then formed over the layer of amorphous silicon and reacted with the layer of amorphous silicon to form a metal silicide structure. The layer of amorphous silicon may have a thickness in the range of about 100 Angstroms to about 3,000 Angstroms, and typically, approximately 1,000 Angstroms. The layer of metal may have a thickness in the range of about 30 Angstroms to about 2,000 Angstroms, and typically, approximately 500 Angstroms. Preferably, the metal may comprise titanium.
The process may further comprise the step of patterning the layers of polysilicon, amorphous silicon and metal to form the interconnect structure. The step of patterning the layers of polysilicon, amorphous silicon and metal to form the interconnect structure may be performed after the step of reacting the layer of amorphous silicon with the layer of metal to form a metal silicide structure. The step of forming a layer of amorphous silicon over the layer of polysilicon comprises the step of doping the layer of amorphous silicon with impurities, such as phosphorous. The layer of amorphous silicon may comprise amorphous silicon hydride.
According to another aspect of the present invention, a process of forming an interconnect structure comprises providing at least one semiconductor layer. A layer of polysilicon is formed over the at least one semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon using plasma enhanced chemical vapor deposition (PECVD) followed by a layer of titanium. The layer of amorphous silicon is then reacted with the layer of metal to form a metal silicide structure. The step of forming a layer of amorphous silicon over the layer of polysilicon using PECVD comprises the step of forming Si and H free radicals by the decomposition of SiH
4
. The step of forming Si and H free radicals through the decomposition of SiH
4
comprises forming silicon hydride having a formula of SiH
x
, where x has a value from about 0.1 to about 5. PECVD is performed in a PECVD reactor, and the value of x is set by controlling at least one of the RF power, the temperature and the pressure of the PECVD reactor.
The step of forming a layer of amorphous silicon over the layer of polysilicon using PECVD may comprise the step of dissolving H
2
in the layer of amorphous silicon. The step of dissolving H
2
in the layer of amorphous silicon is carried out through the decomposition of SiH
4
. An amount of dissolved H
2
may be adjusted by controlling at least one of the RF power, the temperature and the pressure of a PECVD reactor. The step of reacting the layer of amorphous silicon with the layer of metal to form a metal silicide struc

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