Process of forming copper structures

Details Process of forming copper structures Process of forming copper structures

2002-10-24

2004-11-02

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S653000, C438S656000, C438S678000, C438S687000

Reexamination Certificate

active

06812143

ABSTRACT:

FIELD OF THE INVENTION
The invention is directed to a method of depositing copper to form copper structures, particularly copper structures used in semiconductor devices. The invention is also directed to a barrier material and the method of making the same. The barrier material can be used as a barrier layer in integrated circuit structures.
BACKGROUND OF THE INVENTION
In damascene processing, the interconnect structure or wiring pattern is formed within grooves or other openings formed within a dielectric film. Using known techniques a photoresist material is used to define the wiring pattern. The patterned photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. The etched openings are used to define wiring patterns in the dielectric layer. These wiring patterns can extend from one surface of the dielectric layer to the other surface of the dielectric layer. Alternatively, the wiring patterns can be confined to a single layer, that is, not extend to the opposite surface of the dielectric layer. The wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination thereof. Excess metal can then be removed by chemical mechanical polishing through a process known as planarization.
In the single damascene process, via openings are provided in the dielectric layer and filled with a conducting metal, which is often referred to as metallization, to provide electrical contact between layers of wiring levels. In the dual damascene process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with the conducting metal. The dual damascene process can simplify the manufacturing process by eliminating some internal interfaces. Damascene processing followed by metallization is continued for each layer in the electronic component until the electronic device is completed.
Metals are utilized for a variety of applications in semiconductor chips. One such application includes using metals as interconnect structures. One way of forming interconnect structures is electroplating the conducting metal on to semiconductor structures. Recently, copper has started to replace aluminum in interconnect structures in integrated circuit chips. Replacement of aluminum with copper stems at least in part from the lower electrical resistivity of copper. As a result, utilizing copper has resulted in an improvement in IC chip performance. These advantages are described by Luther et al., Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference, 1993, p. 15; and by Edelstein, Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, 1995, p. 301.
One method that may be utilized to deposit copper for chip interconnect structures is the damascene method. See, U.S. Pat. No. 5,612,254, the entire contents of the disclosure of which are incorporated herein by reference. Typically, copper is electroplated to form the structures, as described by Andricacos et al., IBM J. Res. Develop., 42, 567 (1998). Electroplating and the damascene method provide a lower cost versatile method for making copper interconnects.
Electroplated damascene technology begins with the deposition on a semiconductor wafer and patterning of dielectric material. Next, a barrier material is deposited over an entire surface of the wafer including the dielectric material and any underlying portions of the semiconductor wafer exposed by the patterning. The barrier material serves to isolate the silicon circuitry formed in and on the semiconductor wafer from the copper interconnects.
Barrier layer films are needed between the dielectric material and the conductive material in order to prevent atoms of the conductive material from migrating into and at times through the dielectric material and into other active circuit device structures. Migration of conductive material in the device can cause inter-level or intra-level shorts through the dielectric material. Also, junction leakage may result, and threshold voltage (V
t
) levels of the transistors formed within the substrate can shift. In some cases, device functionality can be destroyed.
Migration is a particular concern if copper is used as the interconnect material because copper exhibits relatively high mobility in materials used in semiconductor structures. Yet, in spite of this problem, copper is a favored material for interconnect structures because of its superior conductivity. As a result, if copper is used as an interconnect structures, the copper needs to be confined with a barrier layer.
A barrier material conventionally used in conjunction with copper interconnect structures, is tantalum (Ta) and tantalum nitride (TaN). However, because these barrier materials are more reactive than copper, the formation of contaminating interfacial oxides can result in poor adhesion properties between the deposited copper layer and the barrier material. Due to the presence of the contaminating oxides, these conventional barrier materials usually require the deposition of a Cu seed layer prior to standard Cu electrodeposition in a Cu acid bath.
Other materials that can be used as barrier layer materials in conjunction with copper also exhibit shortcomings. For example, titanium nitride also exhibits poor atomic matching on certain atomic planes along the interface it forms with copper. Also, titanium is generally considered unsuitable for use as a barrier material, because titanium combines with copper to form an inter-metallic compound which lowers the conductivity of the copper film. As a result there is a need for new barrier layer materials that exhibit minimal oxide formation, and improved atomic matching.
Following the deposition of barrier material, a thin conducting layer, generally referred to as a “seed” layer is deposited over the barrier material. This seed layer acts to carry the electrical current for the electroplating process. Although the seed layer can include any conducting metal(s) or metal alloy(s), typically, the seed layer contains copper.
Following the deposition of a seed layer, the metal to make up the interconnect structure can be electrodeposited over the entire surface of the wafer, filling the patterns of lines and vias in the dielectric and simultaneously forming an “overburden” on the top of the dielectric. The overburden can be removed by chemical-mechanical polishing. Electroplating in damascene technologies entails making electrical contact to the seed layer, at one, or preferably, a multiplicity of points at the edge of the substrate. In some kinds of plating tools, the contact area is exposed to the plating solution. Exposure of the seed layer to the plating solution can result in etching of the seed layer, because the plating solution can include very corrosive materials. Any etching of the seed layer the plating bath can imperil the contact and as a result the quality of the electroplated metal.
Furthermore, the ability of electroplating processes to fill damascene patterns, particularly dual damascene patterns, which can have increasingly high aspect ratios as the dimensions of VLSI technology shrink and essentially vertical side walls, is critically dependent on the integrity of the seed layer that carries the plating current. Missing seed layer, whether as a result of problems in deposition or etching by the plating solution can lead to a void in the electroplated metal. Voids in the lines substantially increase their resistance and result in poor reliability.
Still another problem associated with the use of a seed layer is the relative differences in the thickness of the seed layer. In general, the thickness of the seed layer is greatest on top of the dielectric than on the side-walls and bottoms of the lines and vias of a damascene pattern, particularly a dual damascene pattern. Although many advances have been made in the physi

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