Process of forming an ultra-shallow junction dopant layer...

Details Process of forming an ultra-shallow junction dopant layer... Process of forming an ultra-shallow junction dopant layer...

2001-06-06

2002-05-14

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S478000, C438S308000

Reexamination Certificate

active

06387782

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit devices. More particularly, the present invention relates to shallow n
+
and p
+
doped junctions formed within a silicon substrate, and the processes for forming such doped junctions.
BACKGROUND OF THE INVENTION
The formation of ultra-shallow p
+
and n
+
doped regions within the silicon substrate is a crucial step in the fabrication of metal-oxide semiconductor (MOS) transistors and other semiconductor devices used within integrated circuits. The ever-decreasing size of MOS transistors requires a downscaling of all lateral and vertical dimensions of the transistor. In conventional scaling scenarios, the depth of the junctions, which form the source and drain regions of MOS transistors, scales linearly with gate length. Therefore, shallower junctions of p
+
and n
+
regions which have suitably low sheet resistance are required in the present semiconductor manufacturing industry.
In conventional semiconductor manufacturing processes, shallow junctions may be formed by ion implantation followed by an anneal such as a rapid thermal anneal (RTA). The reliability of this technique is known in the art down to a junction depth of 300 to 400 angstroms. The task of producing a doped region having both a junction depth of less than 300 or 400 angstroms and a suitably low sheet resistance is more challenging. This task is rendered particularly difficult for p-type shallow doped regions by the implant and diffusion properties of boron, in particular. Crucial issues include control of dopant channeling, reduction of thermal diffusion, and suppression of transient-enhanced diffusion, especially in the case of boron and phosphorus. Moreover, good device performance is only attained with a low sheet resistance of the shallow regions (i.e., with a high impurity concentration). The scaling tendency has been to reduce the ion implant energy while the total dopant level is kept more or less constant, and to reduce the thermal budget without significantly deteriorating the dopant activation level by introducing rapid thermal anneals and spike anneals.
This conventional scaling is expected to become difficult below the 300 to 400 angstrom junction depths, particularly for p
+
junctions. The technical difficulty in making a high-current, low-energy ion implantation beam may be alleviated by the use of plasma doping (alternatively called plasma immersion ion implantation). Alternative processes that avoid implantation altogether have also been considered. Examples of such processes include rapid thermal vapor phase doping, gas immersion laser doping, and solid state hot diffusion such as from a BSG (boro-silicate glass), PSG (phosphorus silicon glass), or ASG (arsenic silicon glass) film. All of these processes face one or more problems with manufacturability.
Another process for producing doped regions having shallow junctions includes outdiffusion from an implanted oxide. According to this process, a thin oxide on top of the silicon is implanted with a high dose of boron or phosphorus so as to confine the dopant within the oxide. During a subsequent RTA step, the dopant is driven into the silicon. This process relies on a high concentration of boron or phosphorus in the oxide to provide for sufficient dopant diffusion through the Si—SiO
2
interface and into the silicon. Therefore, given the limitations and capabilities of available ion implantation equipment, this process is only practical for use in conjunction with an oxide that is thinner than 100 angstroms. The required high dosage may produce defects within the silicon substrate.
Recent attempts to optimize this process have placed the dopant peak concentration near the top surface of the oxide for fear of creating defects within the silicon, due to high dosage amounts. Such defects may remain within the silicon even after a subsequent annealing process is completed. Recent attempts to use this technique are also limited because nearly all of the implanted species must be implanted into the oxide, and not into the underlying silicon, to avoid the problem of defects. As a consequence, all of the implanted species which diffuse into the silicon during anneal originate from within the oxide film. Because the peak concentration of the implanted species is near the top surface of the oxide film, the annealing process is necessarily a time-consuming process in order to allow for the diffusion of the implanted species from near the upper surface of the oxide film into the silicon. Alternatively, a high dose would be required to achieve a suitably low sheet resistance. Such a high dose is undesirable, however, because defects may result in the silicon substrate.
What is needed is a structure, and a process for producing the structure, that provides a maximum doping of the silicon to produce a suitably low sheet resistance. The process should use a reduced annealing time, a reduced dose, or both a reduced annealing time and a reduced dose with a corresponding reduced implant time. The need is to produce a doped region that has an ultra-shallow junction depth and is substantially defect-free.
SUMMARY OF THE INVENTION
To meet these and other needs, and in view of its purposes, the present invention provides a process and structure that embrace the technique of outdiffusion from an implanted dielectric film. An optimized process is provided in which the peak concentration of the implanted dopant species is closer to the silicon-dielectric interface than as formed by conventional processing attempts. An implant process is provided that uses a higher energy and a lower dose than conventional implant processes targeted at producing the same sheet resistance. The comparatively high energy of the implant process results in the peak concentration being placed closer to the silicon-dielectric interface. The reduced implant dosage and the proximity of the dopant species to the interface prevent the introduction of defects into the silicon, such as dislocation loops and other defect clusters which are not capable of being corrected by a subsequent annealing process.
The process of the present invention produces a structure having a dopant peak concentration in the dielectric and which is closer to the silicon-dielectric interface than the upper surface of the dielectric film. The process includes implanting at least some of the dopant species through the dielectric film and directly into the subjacent silicon. Because some of the implanted species are already in the silicon, and the peak concentration is relatively close to the silicon-dielectric interface, a shorter anneal time is required to drive a significant amount of the implanted dopant species into the silicon and to produce a sufficiently low sheet resistance of the ultra-shallow junction doped region formed within the silicon.
In addition to driving some of the implanted dopant species into the silicon, the anneal process may also move the peak concentration of the implanted species closer to the interface and while using a reduced annealing time. The resulting ultra-shallow junction doped structure includes a high dopant species concentration, a sufficiently low sheet resistance, and virtually no defects because of the proximity of the as-implanted peak concentration to the silicon surface. Such a doped region is particularly useful as a source-drain extension region and finds application in other shallow junction regions which require a shallow junction with a suitably low sheet resistance. The process is manufacturable because of the reduced annealing time and lower dose needed to produce a suitably low sheet resistance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
patent: 5401674 (1995-03-01), Anjum et al.
patent: 5493132 (1996-02-01), Brugge et al.
patent: 5882961 (1999-03-01), Klingbeil, Jr. et al.
patent: 5918140 (1999-06-01), W

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