Process of forming a semiconductor device and a...

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S396000, C438S240000, C438S395000

Reexamination Certificate

active

06518070

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to processes for forming semiconductor devices, and more particularly, to processes for forming semiconductor devices having a deposited layer.
RELATED ART
High-k dielectrics are needed for capacitors used in semiconductor devices having design rules at or below 0.25 micron. A problem in forming these capacitors has been the unintentional oxidation of conductive plugs that are used to electrically connect the capacitors with other circuitry within the semiconductor device. When forming the capacitor, a first electrode is typically deposited over the conductive plug. The first electrode may have materials incompatibility issues with the conductive plug, or the first electrode may not adequately protect the underlying conductive plug from being oxidized during a subsequent deposition process step or an oxidizing anneal process step typically needed for the high-k dielectric.
A conductive barrier layer may be placed between the bottom electrode and the conductive plug. However, most barrier layers do not always adequately protect the conductive plug from being oxidized because oxygen from the subsequent deposition or anneal process can diffuse to the conductive plug and oxidize it. In addition, most conductive barrier layers that are used within the semiconductor industry cannot withstand annealing temperatures higher than approximately 550° C. At higher temperatures, the barrier layer may partially or completely oxidize, thereby forming a series capacitor with the storage capacitor, and therefore, degrading the overall capacitance density of the device. Additionally, severe oxidation of the plug material may result in a catastrophic failure of the device due to the physical expansion of the oxidized plug material.


REFERENCES:
patent: 4337476 (1982-06-01), Fraser et al.
patent: 4506279 (1985-03-01), Mizutani
patent: 4732801 (1988-03-01), Joshi
patent: 5164808 (1992-11-01), Evans, Jr. et al.
patent: 5383088 (1995-01-01), Chappel-Sokol et al.
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5396093 (1995-03-01), Lu
patent: 5407855 (1995-04-01), Maniar et al.
patent: 5428244 (1995-06-01), Segawa et al.
patent: 5489548 (1996-02-01), Nishioka et al.
patent: 5492855 (1996-02-01), Matsumoto et al.
patent: 5576928 (1996-11-01), Summerfelt et al.
patent: 5622893 (1997-04-01), Summerfelt et al.
patent: 5677221 (1997-10-01), Tseng
patent: 5696018 (1997-12-01), Summerfelt et al.
patent: 5858846 (1999-01-01), Tsai et al.
patent: 5891787 (1999-04-01), Gardner et al.
patent: 5895946 (1999-04-01), Hamamoto et al.
patent: 5909043 (1999-06-01), Summerfelt
patent: 5955785 (1999-09-01), Gardner et al.
patent: 5973351 (1999-10-01), Kotecki
patent: 5976928 (1999-11-01), Kirlin
patent: 6030866 (2000-02-01), Choi
patent: 6037264 (2000-03-01), Hwang
patent: 6090697 (2000-07-01), Xing et al.
patent: 6117689 (2000-09-01), Summerfelt et al.
patent: 6153490 (2000-11-01), Xing et al.
patent: 6177351 (2001-01-01), Beratan et al.
patent: 6184550 (2001-02-01), Van Buskirk et al.
patent: 6191470 (2001-02-01), Forbes
patent: 6194754 (2001-02-01), Aggarwal et al.
patent: 6204172 (2001-03-01), Marsh
patent: 6288420 (2001-09-01), Zhang et al.
patent: 6303972 (2001-10-01), Agarwal
patent: 6376355 (2002-04-01), Yoon et al.
patent: 6391769 (2002-05-01), Lee et al.
Saenger et al., “Properties and Decomposition Behaviors of Reactively Sputtered Pt (O) Electrode Materials,” Materials Research Society, Ferroelectric Thin Films VIII, Symposium Y, Nov. 29, 1999.
Saenger et al., “Buried, self-aligned barrier layer structures for perovskite-based memory devices comprising Pt or Ir bottom electrodes on silicon-contributing substrates,” American Institute of Physics, pp. 802-813 (1998).
Khamankar et al., “A Novel BST Storage Capacitor Node Technology Using Platinum Electrodes for Gbit DRAMS,” IEEE, pp. 245-248 (1997).
Onishi et al., “A New High Temperature Electrode-Barrier Technology on High Density Ferroelectric Capcitor Structure,” IEEE, pp. 699-702 (1996).
Grill et al., “Platinum Alloys and Iridium Bottom Electrodes for Perovskite Based Capacitors in DRAM Applications,” Integrated Ferroelectrics, vol. 9, pp. 299-308 (1995).
Grill et al., “Base Electrodes for high dieletric constant oxide materials in silicon technology,” Materials Research Society, pp. 3260-3265 (1992).
Zurcher et al; U.S. patent application Ser. No. 09/022,756 filed Feb. 12, 1998.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process of forming a semiconductor device and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of forming a semiconductor device and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of forming a semiconductor device and a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3177218

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.