Process of forming a bottle-shaped trench

Details Process of forming a bottle-shaped trench Process of forming a bottle-shaped trench

2003-01-03

2004-08-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S386000, C438S424000, C438S704000

Reexamination Certificate

active

06770563

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a bottle-shaped trench fabrication process used in dynamic random access memory (DRAM).
2. Description of the Related Art
As the integration density of dynamic random access memory (DRAM) steadily increases, it becomes necessary to reduce the memory cell size. The memory cell size is primarily determined by the minimum resolution dimension of a lithographic technique, the overlay tolerances between the different features, and the layout of these features. At the same time, it is necessary to maintain the minimum required storage capacitance to reliably operate the DRAM. To meet both the cell size and storage capacitance requirements, a trench capacitor was invented, the simple single device/capacitor memory cell being altered to provide the capacitor in a vertical dimension. In such designs, the capacitor is formed in a trench in the surface of the semiconductor substrate.
However, as the size of a DRAM is scaled down by a factor of f (feature size), the trench storage node capacitance decreases by a factor of f. Therefore, it is important to develop methods to increase the storage capacitance. One method employed to increase capacitance is to widen the bottom portion of the trench, thus, increasing the surface area and creating a “bottle shaped” capacitor.
However, in order to space the capacitors closely, control of the etching process used to widen the bottom portion becomes a governing factor. Chemical dry etching is predominantly used to create the bottle-shaped portion of the capacitor. In U.S. Pat. No. 5,112,771 issued to Ishii, et al. on May 12, 1992, entitled, “METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A TRENCH”, the bottom region of a trench capacitor is enlarged. This is accomplished by leaving a silicon oxide film on the upper sidewall of a trench, and enlarging the width of the exposed bottom portion of the trench by anisotropic dry etching. Since the silicon substrate is isotropically dry etched, it is etched not only per pendicular to the surface of the substrate, but also parallel thereto. Although the capacitor surface area is enlarged, such etching processes are not easily controlled.
In
FIG. 1
, a semiconductor substrate
101
is provided. A pad stack layer
106
is formed on the semiconductor substrate
101
. The pad stack layer
106
is formed by chemical vapor deposition (CVD). For example the pad stack layer
106
is a combination of a pad oxide layer
102
, a nitride layer
103
, and a borosilicate glass (BSG) layer
105
. The pad oxide layer
102
is formed on the semiconductor substrate
101
. The nitride layer
103
is formed on the pad oxide layer
102
. The BSG layer
105
is formed on the nitride layer
103
. The pad stack layer
106
is used as a hard mask layer for etching deep trench step. A mask opening
108
is formed in the pad stack layer
106
to expose a portion of the surface of the semiconductor substrate
101
.
The exposed semiconductor substrate
101
is etched to form a neck profile
109
using a combination gas of HBr, NF3, and a premixed He/O2 as primary plasma gas. The depth of the neck profile
109
is about 1.2 um.
In
FIG. 2
, the trench profile
109
is etched to remove the exposed semiconductor substrate to form a bottom profile
110
using the combination gas of HBr, NF3, and premixed He/O2 as a primary plasma gas.
The conventional process of forming the bottle-shaped trench is not easily controlled, and the quality of the capacitor is rarely satisfactory.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming a bottle-shaped trench in a semiconductor substrate. According to the method, the capacitor surface area can be efficiently enlarged in a is simpler way; a formation method of bottle-shaped trench for capacitor that is easily controlled.
Accordingly, the present invention provides a process of forming a bottle-shaped trench. A semiconductor substrate is provided. A pad layer and a hard mask layer are all sequentially formed on the surface of the semiconductor substrate. A trench is formed in the semiconductor substrate. A dielectric layer is formed on the surface of the hard mask layer. The trench is filled with the dielectric layer. The dielectric layer in the trench is etched to a predetermined depth. A spacer is formed on the sidewall of the trench. The dielectric layer is removed. The trench, unmasked by the spacer, is etched to a bottle shape.
The present invention also provides another process of forming a bottle-shaped trench. A semiconductor substrate is provided. A pad layer, a hard mask layer, and a patterned insulating layer having an opening exposing the surface of the hard mask layer, are all sequentially formed on the semiconductor substrate. The hard mask layer, the pad layer, and the semiconductor substrate are all sequentially etched to form a trench. The patterned insulating layer is removed. A spin-on glass layer is formed on the surface of the hard mask layer, filling the trench. The spin-on glass layer in the trench is anisotropically etched to a predetermined depth, and the spin-on glass layer on the surface of the hard mask layer is totally removed. An insulating layer is conformally formed on the surface of the hard mask layer and the trench. The insulating layer is anisotropically etched to form a spacer on the sidewall of the trench. The surface of the spin-on glass layer is exposed. The spin-on glass layer is removed by wet etching. The trench, unmasked by the spacer, is isotropically etched to a bottle shape.
The present invention also provides yet another process of forming a bottle-shaped trench. A semiconductor substrate is provided. A pad layer and a hard mask layer are all sequentially formed on the semiconductor substrate. A conformal first liner layer and a conformal second liner layer are all sequentially formed on the surface of the hard mask layer and the trench. A dielectric layer is formed on the surface of the hard mask layer, filling the trench. The dielectric layer in the trench is etched to a predetermined depth. A spacer is formed on the sidewall of the trench. The dielectric layer is removed. The exposed second liner layer is removed. The spacer and the exposed first liner layer are removed. The trench, unmasked by the first liner layer and the second liner layer, is etched to a bottle shape.
Accordingly, the present invention also further provides another process of forming a bottle-shaped trench. A semiconductor substrate is provided. A pad layer, a hard mask layer, and a patterned insulating layer having an opening exposing the surface of the hard mask layer are all sequentially formed on the semiconductor substrate. The hard mask layer, the pad layer, and the semiconductor substrate are all sequentially etched to form a trench. The patterned insulating layer is removed. A conformal first liner layer and a conformal second liner layer are all sequentially formed on the surface of the hard mask layer and the trench. A spin-on glass layer is formed on the surface of the hard mask layer, filling the trench. The spin-on glass layer is etched to a predetermined depth. A conducting layer is conformally formed on the surface of the trench and the spin-on glass layer. The conducting layer in the trench is anisotropically etched to form a spacer. The surface of the spin-on glass layer is exposed. The spin-on glass layer is removed by wet etching. The exposed second liner layer is removed. The spacer and the exposed first liner layer are removed. The trench, unmasked by the first liner layer and the second liner layer, is etched to a bottle shape.


REFERENCES:
patent: 5112771 (1992-05-01), Ishii et al.
patent: 6232171 (2001-05-01), Mei
patent: 6486024 (2002-11-01), Tews et al.
patent: 2002/0014647 (2002-02-01), Seidl et al.
patent: 2002/0072171 (2002-06-01), Forster et al.
patent: 2002/0072198 (2002-06-01), Ahn
patent: 2003/0036241 (2003-02-01), Tews

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