Process of fabricating semiconductor device having doped polysil

Details Process of fabricating semiconductor device having doped polysil Process of fabricating semiconductor device having doped polysil

1997-03-04

1999-03-23

Trinh, Michael

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438486, 438657, 438301, H01L 213205

Patent

active

058858890

ABSTRACT:
An intentionally undoped amorphous silicon layer, a phosphorous doped amorphous silicon layer and a tungsten silicide layer are successively laminated on a gate oxide layer, and are patterned into a gate electrode of a field effect transistor; while a phosphosilicate glass layer over the gate electrode is being reflowed, the amorphous silicon layers are crystallized to a polysilicon layer, and phosphorous is less segregated at the boundary between the gate oxide layer and the polysilicon layer during the heat treatment.

REFERENCES:
patent: 5081066 (1992-01-01), Kim
patent: 5155051 (1992-10-01), Noguchi
patent: 5242855 (1993-09-01), Oguro
patent: 5486237 (1996-01-01), Sano et al.
patent: 5639689 (1997-06-01), Woo

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