Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-02-16
2001-01-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S270000, C438S222000, C257S347000, C257S397000
Reexamination Certificate
active
06180486
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a silicon-on-insulator (SOI) structure and, more specifically, to a planar, densely patterned SOI structure and to a process for fabrication of such a structure.
BACKGROUND OF THE INVENTION
Patterned SOI (silicon-on-insulator) structures consist of SOI and non-SOI (or bulk) areas. Patterned SOI structures are useful for circuits that require both conventional and SOI devices. Such circuits include, for example, Merged Logic Dynamic Random Access Memory (ML-DRAM) circuits.
One process used to create patterned SOI wafers involves the deposition of epitaxial silicon (selective epi process) into selectively formed trenches. The development of the capability to etch narrow trenches in silicon substrates has increased the importance of the selective epi process. If these narrow trenches can be successfully filled with a silicon material, then it is possible to form closely spaced silicon islands isolated by an insulating layer such as an oxide.
The first step in forming closely spaced silicon islands isolated by an insulating layer is the formation of trenches. In this step, the SOI substrate is selectively etched down to the surface of the base layer in the area where non-SOI substrate is desired, forming a trench. Next, selective epi processing fills the trench.
This method uses epitaxial silicon growth which is selective to exposed silicon, primarily the exposed silicon wafer at the bottom of the etched trench. Selective epitaxial deposition is achieved when silicon atoms possessing high surface mobility migrate to single silicon crystal sites where nucleation is favored. As a result of this selective epi processing, the trench is filled with silicon. The resulting structure comprises an SOI area and a non-SOI area having a trench filled with silicon.
Unfortunately, several problems can arise in performing the selective epi process. One problem is the formation of a damaged silicon crystal structure. This problem is the result of having two or more sources of growth. During epitaxial silicon growth in the trench, it is highly preferable to grow silicon from a single source. An objective of selective epi processing is to fill the trench with silicon having the same crystal lattice structure as the underlying silicon wafer so that, in effect, the silicon filling the trench is an extension of the silicon wafer. When there are two or more sources of silicon growth, the resulting epitaxial silicon grown is damaged because the silicon tends to grow at differing rates and orientations. Thus, the desired uniform silicon crystal structure is not achieved.
A second problem is the formation of bumps. When epitaxial silicon is grown on the silicon layer portion of the trench side wall, a bump is formed between the SOI area and the non-SOI area. This bump has several drawbacks. The most serious consequence is the decreased ability to make small, densely patterned SOI and non-SOI areas. Moreover, these bumps are an obstacle in subsequent planarization steps, often forcing costly and time consuming additional processing steps.
The deficiencies of the use of selective epi processing to fill trenches show that a need still exists for eliminating epitaxial growth of silicon originating from the silicon layer portion of the trench side walls. To overcome the shortcomings of selective epi processing, a new process is provided. An object of the present invention is to provide a process of filling a trench using selective epi processing, in which the process forms the desired uniform crystal structure of the underlying silicon layer and also does not create bumps between the SOI and non-SOI areas.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a process for fabricating a planar SOI structure having areas devoid of buried oxide. Using the selective epitaxial process, a planar SOI structure is formed having a trench filled with a uniform crystal structure matching the crystal lattice structure of the underlying silicon wafer. In addition, the present invention limits the formation of bumps between the SOI area and non-SOI area of the planar SOI structure.
The SOI structure of the present invention comprises a silicon wafer, an oxide layer, and a silicon layer. The structure has trenches extending from the top surface of the structure to the silicon wafer and being filled with a semiconductor. The trenches have a top, a bottom, and side walls with side-wall silicon portions. The silicon side-wall portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layer from the trench top to the trench bottom.
In forming a planar SOI structure of the present invention, a substrate is first obtained having a silicon wafer, an oxide layer, a silicon layer, and a nitride layer. The substrate has a top surface. The process comprises the following steps:
(a) forming a trench in the substrate extending from the substrate top surface to the silicon wafer, the trench having side walls and a bottom, the trench side walls having side-wall silicon portions;
(b) forming an oxide layer on the trench bottom and an oxide layer on the side-wall silicon portions to form a trench bottom oxide layer and trench side-wall oxide layers;
(c) forming a protective side wall on the trench side wall extending over the trench side-wall oxide layer and overlying a portion of the trench bottom oxide layer;
(d) removing all of the trench bottom oxide layer not underlying the protective side wall; and
(e) filling the trench with a semiconductor to at least the top surface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Leobandung Effendi
Sadana Devendra K.
Schepis Dominic J.
Shahidi Ghavam
Abate Esq. Joseph P.
Blum David S
Bowers Charles
International Business Machines - Corporation
Ratner & Prestia
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