Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-10-01
2003-11-04
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S612000, C438S613000, C438S614000, C438S615000
Reexamination Certificate
active
06642079
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to flip chip interconnection structure and a manufacture process of the flip chip interconnection structure that prevent spalling effects. More particularly, the invention forms a composite intermetallic compound in the flip chip interconnection structure to prevent spalling effects.
2. Description of the Related Art
In response to the concern of environmental pollution by lead (Pb) which seriously affects human health, the industrialized countries have implemented restrictive standards to reduce as much as possible the use of lead-containing substances in industrial products and manufacture processes. In some aspects, those restrictions have met successful results such as, for example, the developments of automobile lead-free fuel and lead-free paint products. In other aspects such as electronic products, more restrictions are expected to accelerate the ban of lead-containing substances in manufactured products. In this purpose, the Ministry of Trade and Industry of Japan has already passed a regulation that prohibits the sale of electric and electronic products in Japan that contain lead substances after the year of 2002. The European Commission proposes the implementation of similar restrictive measures after the year of 2007. Therefore, the particular development of lead-free solder materials, solder materials being widely used in the microelectronic and semiconductor industries, appears to be a technical necessity for the manufacturers that want to conform to the future national and international anti-pollution legislation.
In the semiconductor packaging process, the use of lead-free solder material has met concrete developments in respect of certain aspects such as for attachments of ball grid array (BGA) packages or surface mount dies. However, many problems remain with respect to some particularly critical techniques that require the use of lead-containing substances. For example, to achieve a controlled collapse chip connection (C
4
), the skilled artisan knows that the use of lead-free solder material for the connecting bumps between the chip and the carrier substrate causes spalling effects of the UBM layer. This consequently deteriorates in substantial manner the strength of the solder joint within the flip chip interconnection structure.
FIG. 1
is a schematic view that illustrates a conventional flip chip interconnection structure. As illustrated, a conventional flip chip interconnection structure usually attaches a chip
100
through bumps
108
to a carrier substrate
110
. An underfill material
114
is further filled between the chip
100
and the carrier substrate
110
to buffer the mechanical stresses induced in the bumps
108
due to thermal mismatch between the chip
100
and the carrier substrate
110
.
An active surface
100
a
of the chip
100
includes bonding pads
102
and a passivation layer
104
that has openings
105
exposing the bonding pads
102
. The carrier substrate
110
includes contact pads
112
that correspond to the bonding pads
102
. To achieve a flip chip interconnection through the bumps
108
, an under bump metallization (UBM) layer
106
is commonly interfaced between each bonding pad
102
and bump
108
.
A structure of UBM layer
106
known in the prior art comprises a chromium (Cr) layer
106
a
, a copper (Cu) layer
106
b
and a gold (Au) layer
106
c
, while the bumps
108
are commonly made of a solder material. After the UBM layers
106
and the solder material of the bumps
108
have been formed, the chip
100
is mounted on the carrier substrate
110
and a reflow process is performed to turn the solder material to solder bumps
108
.
Besides Cr/Cu/Au triple-layers structure, a double-layers structure of the UBM layer comprising chromium
ickel is also known in the prior art. When the UBM layer comprises a triple-layers structure of Cr/Cu/Au, tin (Sn) in the solder material will typically react with copper of the UBM layer to form copper-tin (Cu—Sn) intermetallic compound. In the case of a double-layers structure Cr/Ni of the UBM layer, tin (Sn) of the solder material will typically react with nickel (Ni) of the solder material to form a tin-nickel (Sn—Ni) intermetallic compound.
Regardless whether it is composed of Cu—Sn compound or Sn—Ni compound, the known intermetallic compound has high interfacial energy with chromium of the UBM layer. As a result, during reflowing, the Cu—Sn or Sn—Ni intermetallic compound spalls and becomes spherical, and then-peels from the surface of the chromium layer of the UBM layer to flow into the solder material. This spalling and peeling effect seriously deteriorates the strength of the solder joint in the flip chip package.
SUMMARY OF THE INVENTION
An aspect of the invention is therefore to provide a flip chip interconnection structure and a process for fabricating the same flip chip interconnection structure, in which a composite intermetallic compound is formed to prevent spalling effects.
To accomplish the above and other objectives, a flip chip interconnection structure of the invention comprises at least a tin-containing solder bump that is selectively formed between a bonding pad of an electronic chip and a contact pad of a carrier substrate. The tin-containing solder bump is formed on an under bump metallization (UBM) layer itself formed on the bonding pad of the chip. A composite intermetallic is interfaced between the tin-containing solder bump and the UBM layer to prevent the occurrence of spalling effects of the UBM layer. An underfill material is further filled between the chip and the carrier substrate to encapsulate the tin-containing solder bump.
In accordance with the above and other objectives, the invention further provides a manufacture process of a flip chip interconnection structure suitable for flip chip bonding of an electronic chip to a carrier substrate. A UBM layer is formed on at least a bonding pad of the chip, and a tin-containing solder material is formed on the UBM layer. The chip is mounted on the carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A copper reservoir is further provided in proximity of the tin-containing solder material. A reflow process then is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound between the tin-containing solder bump and the UBM layer to prevent spalling effects.
According to a preferred embodiment of the invention, the UBM layer includes a nickel (Ni) layer that reacts with tin (Sn) of the solder material and copper (Cu) of the copper reservoir during reflowing to form the composite intermetallic compound. A portion of the composite intermetallic compound adjacent to the UBM layer thereby includes Cu
6
Sn
5
while a portion of the composite intermetallic compound adjacent to the tin-containing solder bump includes (Cu, Ni)
6
Sn
5
. Via the formation of this composite intermetallic compound, the nickel layer of the UBM layer is isolated from the solder material, which therefore prevents spalling of the UBM layer.
According to one aspect of the invention, the copper reservoir is constituted via introducing copper particles in the tin-containing solder material formed on the UBM layer.
According to another aspect of the invention, the copper reservoir is constituted via having the contact pad of the carrier substrate made of copper.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5470787 (1995-11-01), Greer
patent: 6127736 (2000-10-01), Akram
patent: 6163463 (2000-12-01), Marrs
patent: 6224690 (2001-05-01), Andricacos et al.
patent: 6492197 (2002-12-01), Rinne
patent: 6501185 (2002-12-01), Chow et al.
patent: 2002/0093096 (2002-07-01), Tago et al.
patent: 2003/0013290 (2003-01-01), Greer
Kao Cheng-Heng
Liu Cheng-Yi
Wang Shen-Jie
Duong Khanh B.
Jiang Chyun IP Office
National Central University
Zarabian Amir
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