Process of fabricating field effect transistor having reliable p

Details Process of fabricating field effect transistor having reliable p Process of fabricating field effect transistor having reliable p

1996-06-24

1997-12-23

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438305, H01L 213205

Patent

active

057007349

ABSTRACT:
A field effect transistor has a polycide structure having a doped polysilicon strip on a gate oxide layer and a crystal tungsten silicide strip on the doped polysilicon strip, and the polycide structure is formed through a process sequence having the steps of patterning an amorphous tungsten silicide layer into an amorphous tungsten silicide strip, crystallizing the amorphous tungsten silicide strip and patterning a doped polysilicon layer into the doped polysilicon strip, thereby preventing the crystal tungsten silicide strip from undesirable warp without contamination of the gate oxide layer.

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patent: 5441914 (1995-08-01), Taft et al.
"Degradation of MOS Characteristics Caused by Internal Stresses in Gate Electrodes" Yamamoto; Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 415-418.

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