Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1994-12-19
1999-07-27
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438639, 438740, 438970, H01L 2128
Patent
active
059306688
ABSTRACT:
A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed in it by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, electrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures. A variety of deposition methods are set forth including methods employing an anisotropic etch and methods employing an etch-stop/masking layer. Resulting structures are also described.
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Intel Corporation
Kaplan David J.
Quach T. N.
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