Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-30
2003-09-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S131000, C438S701000, C438S978000
Reexamination Certificate
active
06617233
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90127983, filed Nov. 12, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a structure of a semiconductor device and a process of fabricating the same. More particularly, the invention relates to a process of fabricating an anti-fuse.
2. Description of the Related Art
Anti-fuses, in a gate array of a logical circuit, are used to connect all transistors, respectively. In other words, each of the transistors, in the gate array, is provided with one of the anti-fuses to connect respectively with the other transistors, and the function of the anti-fuses is to make the gate array programmable. A conventional anti-fuse is a structure of metal layer-dielectric layer-metal layer. The current structure of an anti-fuse further includes a passivation layer between the dielectric layer and the metal layer such that the dielectric layer can be protected and not destroyed by a following etching process. When a gate array is being programmed using an anti-fuse, a high voltage is applied to the anti-fuse in such a way that the dielectric layer of the anti-fuse is broken-down and, thus, the anti-fuse is in an open state. On the contrary, if no voltage is applied to the anti-fuse, the anti-fuse is in a closed state. Therefore, the process of programming with anti-fuses is by applying a voltage or no voltage to the anti-fuses and so making them in an open or closed state, in order to achieve the objective of programming a gate array.
Schematic cross-sectional views of a fabricating process of a conventional anti-fuse are shown from
FIG. 1A
to FIG.
1
E.
As shown in
FIG. 1A
, in the conventional anti-fuse, an inner metal dielectric layer
104
is formed on a substrate
100
provided with a conductive layer
102
, and a via
106
is formed. Subsequently, a tungsten layer
108
is formed over the substrate
100
and filled into the via
106
. However, with the development of device size becoming smaller and smaller, when the tungsten layer
108
is being formed in the via
106
, a suspending protrusion forms at a top edge of the via
106
, such that a key hole
110
is formed. However, the key hole
110
is not easily removed.
Subsequently, as shown in
FIG. 1B
, a tungsten chemical mechanical polishing process (WCMP) is performed in such a way that the tungsten layer
108
outside the via
106
is removed, and then a metal plug
108
a
is formed. However, the tungsten chemical mechanical polishing process, used to perform planarization, causes the surface
112
of the metal plug
108
a
to become rough. Therefore, a physical polishing process is next performed to make the surface
112
smooth.
Next, as shown in
FIG. 1C
, an oxide chemical mechanical polishing process (Oxide CMP) is performed to smooth the surface
112
of the metal plug
108
a
. However, in the process, the key hole
110
of the metal plug
108
b
appears on the surface
112
a.
Subsequently, as shown in
FIG. 1D
, after a dielectric layer
114
is covered on a top side of the metal plug
108
b
, a titanium nitride passivation layer is formed on the dielectric layer
114
, which thus protects the dielectric layer
114
so it is not destroyed by a conductive layer formed in a following process. However, because the key hole
110
appears on the metal plug
108
b
, a tip
118
is formed on a top side of the dielectric layer
114
.
Finally, as shown in
FIG. 1E
, an oxide layer
120
, provided with a via
122
, is formed over the substrate
100
, and the via
122
is positioned on the titanium nitride passivation layer
116
. Lastly, a conductive layer
124
is formed over the substrate
100
and filled into the via
122
.
Accordingly, because the small-size via of the conventional anti-fuse has a steep profile, the key hole can not be prevented when the metal plug is formed in the via. Therefore, the key hole, after a planarization process is performed, usually appears on the metal plug, and thus the tip is formed on the top side of the dielectric layer of the anti-fuse. The tip is a leakage-current source of the anti-fuse.
In order to avoid the above problem, a key size of a big and tapered shape is applied to improve the key-hole problem. However, as the size of the anti-fuse increases, this leads to an impact on the ability to shrink the device in the future.
SUMMARY OF THE INVENTION
Therefore, it is an objective according to the present invention to provide a process of fabricating an anti-fuse while preventing a key hole appearing on a metal plug in the anti-fuse.
It is another objective according to the present invention to provide a process of fabricating an anti-fuse while avoiding a tip formed on a top side of a dielectric of the anti-fuse.
It is another objective according to the present invention to provide a process of fabricating an anti-fuse while reducing a leakage current thereof.
It is another objective according to the present invention to provide a process of fabricating an anti-fuse while avoiding the key size of the big and tapered shape according to the prior art, and so avoiding increasing anti-fuse size.
To achieve the foregoing and other objects, the present invention provides a process of forming an anti-fuse. First, an inter-metal dielectric layer is formed on a substrate and a funnel-shaped via is formed in the inter-metal dielectric layer. Next, a first conductive layer is formed over the substrate and the first conductive layer is filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer such that the dielectric layer can be protected and not be destroyed by a second conductive layer formed in a following process. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer provides a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and the second conductive layer is filled into the via.
According to the present invention, the funnel-shaped via acts as the hole, into which the conductive layer is filled. Because, the funnel-shaped via has a relatively wide dimension at an open end thereof and a relatively narrow dimension at a bottom end thereof, a key hole is only formed in the bottom side of the relatively narrow portion of the funnel-shaped via, such that the key hole does not appear on the conductive plug of the anti-fuse. Therefore, the leakage current of the anti-fuse drops, and the size of a big and tapered shape is not applied to the anti-fuse, which thus cures the defect of increasing the size of the anti-fuse.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5364817 (1994-11-01), Lur et al.
patent: 5763898 (1998-06-01), Forouhi et al.
patent: 6174796 (2001-01-01), Takagi et al.
Guo Ruey Jiunn
Hsieh Tsong-Minn
Fourson George
Maldonado Julio J.
United Microelectronics Corp.
Wu Charles C. H.
Wu & Cheung, LLP
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