Process monitor test chip and methodology

Details Process monitor test chip and methodology Process monitor test chip and methodology

1996-07-12

1998-11-03

Brock, Michael

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

438 18, 257 48, G01R 3128

Patent

active

058314466

ABSTRACT:
A process monitor test chip and methodology allows process-related manufacturing defects to be quickly identified and isolated. A basic circuit block of a test chip having a number of inverter cells serially connected with a corresponding number of observation points before the input of each inverter cell provides for the inverter cells in the basic circuit block to be probed and thus observed by e-beam technology. Any required number of basic circuit blocks may be serially connected end to end to constitute a chain circuit. Within the test chip itself, a plurality of chain circuits may be connected serially or in parallel to accomplish different testing goals. By controlling an input signal and a control signal of a multiplexing element associated with each chain circuit, the plurality of chain circuits can be forced into a serial connection or a parallel connection. In a serial mode, the plurality of chain circuits are serially connected with one input signal and one output signal of the test chip; the serial connection may be used during burn-in of the test chip to test for whether the test chip contains any process-related manufacturing defects. Once it has been determined that the test chip does contain process-related manufacturing defects, the parallel connection allows the defects of the test chip to be quickly isolated.

REFERENCES:
patent: 5132614 (1992-07-01), Sakumoto et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5500603 (1996-03-01), Le
patent: 5563524 (1996-10-01), Ungar

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