Process method for 1T-SRAM

Details Process method for 1T-SRAM Process method for 1T-SRAM

2002-10-03

2004-01-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S210000, C438S239000, C438S245000, C438S248000, C438S381000, C438S386000, C438S391000, C257S068000, C257S071000, C257S260000, C257S277000, C257S516000

Reexamination Certificate

active

06682982

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to fabrication of 1T-SRAMs.
BACKGROUND OF THE INVENTION
Integration of memory in system-on-chip is further complicated by the incompatibility of memory process technology with the logic process. The simplicity of a one transistor-static random access memory (1T-SRAM) cell facilitates its easy porting to most processes. This helps alleviate the problem of process incompatibility. The simplicity of the 1T-SRAM cell also makes it very scalable and cost effective.
However, the 1T-SRAM cell process design needs to be compatible with the logic process with a lower thermal budget requirement while continuing to shrink the device size. Therefore a buried storage node, like a DRAM trench, on a shallow trench isolation (STI) structure and the word line overlying the buried storage node is one of the 1T-SRAM cell design processes. This design will meet the smaller cell size, but it will suffer from a high step height for the cell transistor gate and leakage between the transistor and storage node.
U.S. Pat. No. 6,256,248 B1 to Leung describes a method and apparatus for increasing the time available for internal refresh for 1T-SRAM compatible devices.
U.S. Pat. No. 6,303,502 B1 to Hsu et al. describes a 1T memory device and process.
U.S. Pat. No. 5,374,580 to Baglee et al. describes a 1T memory process.
U.S. Pat. No. 5,073,515 to Roehl et al. describes another 1T memory process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming a cell memory structure.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having an isolation trench formed therein is provided. An isolation structure is formed within the isolation trench. A pad oxide layer is formed over the substrate and the isolation structure. A first dielectric layer is formed over the pad oxide layer. The first dielectric layer, the pad oxide layer and the isolation structure are patterned to form at least: 1) an initial node within the isolation trench; a portion of the initial node having an overlying patterned pad oxide layer portion and an overlying patterned first dielectric layer portion; and 2) patterned first dielectric portions having underlying pad oxide layer portions over the substrate adjacent the isolation trench. A bottom dielectric layer is formed over: the initial node; the substrate; and the patterned first dielectric layer portions over the substrate. A portion of the bottom dielectric layer is removed, leaving a partially removed bottom dielectric layer overlying at least: the isolation trench; the initial node; and any exposed substrate adjacent the isolation trench. A planarized second dielectric layer is formed over the structure at least filling isolation trench and overlying the initial node and the patterned first dielectric layer portions over the substrate. A portion of the planarized second dielectric layer is removed leaving only recessed portions of the second dielectric layer within isolation trench. Then removing: i) a portion of the bottom dielectric layer overlying the initial node adjacent the patterned first dielectric layer portion, leaving a portion of the initial node exposed; and ii) the patterned first dielectric layer portion from the initial node. Removing: the second dielectric layer recessed portions; the patterned pad oxide layer portion overlying the initial node; and the exposed portion of the initial node to leave a final node. A cap dielectric layer is formed over the structure. A top plate dielectric layer is formed over the cap dielectric layer and at least filling the isolation trench, overlying the final node and the patterned first dielectric layer portions over the substrate. The top plate dielectric layer is planarized, stopping on the patterned first dielectric layer portions over the substrate. An ARC layer is formed over the planarized top plate dielectric layer. Patterning: the ARC layer; and the patterned first dielectric layer portions over the substrate to expose side walls, stopping on the underlying pad oxide layer portions. Forming sidewall spacers on the exposed side walls of the twice patterned first dielectric layer portions over the substrate, leaving peripheral portions of the underlying pad oxide layer exposed. The peripheral exposed portions of the underlying pad oxide layer are removed to leave remaining pad oxide layer portions and forming the cell memory structure.


REFERENCES:
patent: 5073515 (1991-12-01), Roehl et al.
patent: 5374580 (1994-12-01), Baglee et al.
patent: 5867420 (1999-02-01), Alsmeier
patent: 6100131 (2000-08-01), Alsmeier
patent: 6256248 (2001-07-01), Leung
patent: 6303502 (2001-10-01), Hsu et al.
patent: 6399977 (2002-06-01), Alsmeier
patent: 6509599 (2003-01-01), Wurster et al.
patent: 6528367 (2003-03-01), Lee
patent: 6566190 (2003-05-01), Lee et al.
patent: 6569747 (2003-05-01), Achuthan et al.
patent: 2003/0042524 (2003-03-01), Lee et al.

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