Process-insensitive self-biasing phase locked loop circuit...

Details Process-insensitive self-biasing phase locked loop circuit... Process-insensitive self-biasing phase locked loop circuit...

2008-04-15

2008-04-15

Chang, Joseph (Department: 2817)

Oscillators

With particular source of power or bias voltage

C331S017000

Reexamination Certificate

active

07358827

ABSTRACT:
A process-insensitive self-biasing PLL circuit and self-biasing method thereof prevent deterioration of loop stability even when there is a fabrication process variation. The self-biasing PLL circuit includes a phase frequency detector, a main charge pump circuit, an auxiliary charge pump circuit, a first operational amplifier, a second operational amplifier, a voltage-controlled oscillator, a divider, and a bias circuit. In the self-biasing PLL circuit, the first operational amplifier amplifies the voltage of a loop filter capacitor and the second operational amplifier serving as a regulator amplifies the output voltage of the first operational amplifier. The output voltage of the second operational amplifier is used as a control voltage of the voltage-controlled oscillator. Particularly, the bias circuit generates a first bias current using an NMOS transistor, generates a second bias current using a PMOS transistor, and sums up the first and second bias currents to generate a third bias current in response to the output voltage of the second operational amplifier. The first bias current is provided to the main charge pump circuit and the auxiliary charge pump circuit as their bias currents, and the third bias current is provided to the first operational amplifier as its bias current.

REFERENCES:
patent: 5334953 (1994-08-01), Mijuskovic
patent: 6710670 (2004-03-01), Maneatis
patent: 7042277 (2006-05-01), Cranford et al.
patent: 2005/0068073 (2005-03-01), Shi et al.
patent: 2000-269810 (2000-09-01), None
patent: 2001-326574 (2001-11-01), None
patent: 2004-112157 (2004-04-01), None
Kun-Yung Ken Chang, et al., “Quad Transceiver Cell Using On-Chip Regulated Dual Loop PLLs”, IEEE Journal of Solid-State Circuits, vol. 38, No. 5, May 2003, S. pp. 747-754.

Affiliated with

Also associated with

Rating

Process-insensitive self-biasing phase locked loop circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process-insensitive self-biasing phase locked loop circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process-insensitive self-biasing phase locked loop circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2791452