Process insensitive ESD protection device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S341000, C257S360000

Reexamination Certificate

active

07368786

ABSTRACT:
Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

REFERENCES:
patent: 2004/0159891 (2004-08-01), Nakamura et al.
Parthasarathy et al., “A Double RESURF LDMOS with Drain Profile Engineering for Improved ESD Robustness,” IEEE Electron Device Letters, vol. 23, No. 4, Apr. 2002, pp. 212-214.
Parthasarathy et al., “Drain Profile Engineering of RESURF LDMOS Devices for ESD Ruggedness,” IEEE Power Semiconductor Devices and ICs, 2002, pp. 265-268.

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