Process improvement for the creation of aluminum contact bumps

Details Process improvement for the creation of aluminum contact bumps Process improvement for the creation of aluminum contact bumps

2001-03-16

2002-11-12

Nguyen, Vinh P. (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S614000, C438S634000, C438S699000

Reexamination Certificate

active

06479376

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a improved method of providing aluminum contact bumps on a semiconductor surface.
(2) Description of the Prior Art
The conventional method that is used for the creation of semiconductor devices simultaneously creates numerous devices and device features on the surface of a semiconductor substrate, after the devices in or on the surface of the substrate have been completed the substrate is cut (diced) for the formation of individual die. The device circuitry that is internal to the device is connected to device input/output (I/O) points of electrical contact. These I/O points of electrical contact to the die must, after the individual die has been created, be further connected to either other semiconductor devices or to a packaging interface. A completed and diced semiconductor die can be connected at a first or card level, which can be further connected to a second or board level of interconnect.
A number of different techniques are used to further interconnect a completed semiconductor device. Wire bonding is frequently used for this purpose, where a (for instance) gold wire is bonded to I/O points of interconnect of the device. Another frequently applied interconnect method uses Tape Automatic Bonding (TAB), wherein the device is attached to an underlying flexible tape in the surface of which points of contact have been provided. The tape typically contains interconnect lines or traces that further route the device I/O points to other points of interconnect. Yet another method uses contact or solder bumps that are provided for this purpose on a surface, for instance the surface of a metal panel or the surface of a printed circuit board. The interconnect in this case is achieved by flowing the solder of the solder bump, fusing two points of electrical contact together and establishing electrical continuity. This latter method is frequently referred to, due to the nature in which the electrical continuity is established, as the Controlled Collapse Chip Connection or C
4
. For all these methods that are used to further interconnect completed and diced semiconductor devices, it is clear that distinct and well identifiable points of contact must be provided through which the electrical continuity is established.
The continuing decrease in semiconductor device feature size, a decrease that is driven by the dual requirements of improved device performance and reduced device manufacturing cost, has over the years resulted in placing increased emphasis on device packaging. This trend has further, due to a significant increase in semiconductor device density, placed increased emphasis on device or package I/O capabilities. The metal connections, which connect the Integrated Circuit to other circuit or system components, have therefore become of relative more importance and potentially have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. If the parasitic capacitance and resistance of the metal interconnections increases, the chip performance can be significantly degraded. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
Packaging requirements have influenced and driven not only internal device design aspects but have in addition led to a number of different approaches of creating the arrays of I/O points that are required to interconnect the device. These different approaches of making I/O points of interconnect available have led to a number of different device types, most notably the Ball Grid Array (BGA) device, the flip chip and the Slightly Larger than Integrated Circuit Carrier (SLICC). Other device configurations are known as Land Grid Array (LGA) devices, Pin Grid Array (PGA) devices, Chip Scale Packaging (CSP) devices and Quad Flat Pack (QFP) devices.
Some of these devices will be briefly highlighted since the method in which these devices are further interconnected relates to the invention.
BGA devices are provided with an array of solder balls that is arranged across the active surface of the die. The solder balls are positioned above and make contact with points of electrical contact that have been provided in a higher level of interconnect, such as a printer circuit board or a metal panel. By flowing the solder balls of the BGA device after contact has been established to the higher level of interconnect, the BGA device is electrically connected to the higher level of interconnect.
Flip chip attachments make use of the design of the flip chip. Points of electrical contact have been provide in the upper surface of the chip, the chip is turned upside down (inverted or flipped), the contact points that have been provided in the upper surface of the chip now face downwards and can be aligned with contact points that have been provided in an underlying interconnect interface such as a metal panel or a printed circuit board. The contact points in the underlying interconnect interface are typically connected to conductive traces for further routing of the interconnection that is provided for the flip chip. By providing and flowing a solder flux to the interfaces between the flip chip and the underlying interconnect interface, electrical contact between these two entities is established.
The SLICC device is similar to the BGA device with the exception that the pitch and the diameter of the solder balls of the BGA is reduced, allowing for increased I/O interconnect.
Many of the I/O interconnect methods, some of which have been highlighted above, use a solder bump as the essential means of creating the interconnect. A conventional procedure for forming a solder bump will be briefly highlighted following.
The procedure starts with a semiconductor surface that has been provide with a for instance aluminum point of electrical contact in the surface thereof. A layer of passivation is deposited over the surface, the layer of passivation is patterned and etched creating an opening in the layer of passivation that aligns with the aluminum contact point in the semiconductor surface. A barrier and/or seed layer can next be deposited over the surface of the layer of passivation, including the inside surfaces of the opening that has been created in the layer of passivation. The surface of the metal barrier layer must next be prepared for the deposition of the solder bump. For this purpose, an etch resistant layer is deposited over the surface of the metal barrier and patterned, creating an opening in the etch resistant layer that aligns with the point of electrical contact. Next, the material that is used for the solder bump is deposited by methods of plating or lamination over the surface of the etch resistant material, filling the opening with the material of the solder bump. The surface of the solder bump material can be polished down to the surface of the etch resistant layer. The etch resistant layer is then removed leaving the solder bump in place overlying the point of electrical contact in the semiconductor surface and electrically connected therewith.
A second method, following Chien et al., U.S. Pat. No. 6,130,149 will also be highlighted. This method addresses forming a cubical aluminum bump on the surface of an integrated circuit chip. This method starts with the surface of a semiconductor substrate, semiconductor devices have been created in or on the surface of the substrate, points of electrical contact to the devices have been made available in the surface of the substrate. A layer of aluminum is deposited over the surface of the substrate, this layer of aluminum is patterned and etched leaving a layer of patterned aluminum overlying points of electrical contact in the surface is the substrate. It must be realized in this that a number of layers of dielectric may be interposed between

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