Static information storage and retrieval – Systems using particular element – Flip-flop
Patent
1992-12-11
1994-12-27
LaRoche, Eugene R.
Static information storage and retrieval
Systems using particular element
Flip-flop
257277, 257300, 437 40, 437 41, 437 52, 437984, G11C 1300
Patent
active
053771397
ABSTRACT:
The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.
REFERENCES:
patent: 4355455 (1982-10-01), Boettcher
patent: 4532609 (1985-07-01), Iizuka
patent: 4535426 (1985-08-01), Arlizumi et al.
patent: 4590508 (1986-05-01), Hirakawa et al.
patent: 4679171 (1987-07-01), Logwood et al.
patent: 4725981 (1988-02-01), Rutledge
patent: 4729002 (1988-03-01), Yamazaki
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 4879690 (1989-11-01), Anami et al.
patent: 5073510 (1991-12-01), Kwon et al.
patent: 5132771 (1992-07-01), Yamanaka et al.
patent: 5135881 (1992-08-01), Saeki
patent: 5145799 (1992-09-01), Rodder
patent: 5240872 (1993-08-01), Motonami et al.
patent: 5264391 (1993-11-01), Son et al.
Wang; "High Performance, High Density Capacitively Loaded FET Static RAM"; IBM Tech. Discl. Bulletin; vol. 27, No. 4A; pp. 1950-1951 (1984).
Yamanaka, et al.; "A 25 .mu.m2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity"; IEDM; pp. 48-51 (1988).
Itabashi, et al.; "A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts"; IEDM; pp. 477-480 (1991).
Chappell, et al.; "Stability and SER Analysis of Static RAM Cells"; IEEE Trans. on Electron Dev.; vol. ED-32, No. 2, pp. 463-470 (1985).
Baker Frank K.
Cooper Kent J.
Hayden James D.
Lage Craig S.
LaRoche Eugene R.
Meyer George R.
Motorola Inc.
Niranjan F.
LandOfFree
Process forming an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process forming an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process forming an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-923360