Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1998-06-25
1999-11-09
Graybill, David E.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438611, 438612, 438652, 438667, 438669, 438675, 438686, 438687, 438759, 438780, 438599, 438121, 438125, H01L 2158, H01L 2148, H01L 2128, H01L 21304
Patent
active
059813113
ABSTRACT:
A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.
REFERENCES:
patent: 5010038 (1991-04-01), Fox et al.
patent: 5346861 (1994-09-01), Khandros et al.
patent: 5407864 (1995-04-01), Kim
patent: 5646067 (1997-07-01), Gaul
patent: 5770476 (1998-06-01), Stone
Chia Chok J.
Lim Seng Sooi
Variot Patrick
Graybill David E.
LSI Logic Corporation
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