Electrical computers and digital processing systems: support – Synchronization of plural processors
Reexamination Certificate
2007-03-20
2007-03-20
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of plural processors
C713S400000, C375S354000
Reexamination Certificate
active
10866097
ABSTRACT:
A method for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps indicating the time and at least one second clock which has an adjustable clock rate is synchronised with the first clock at certain time intervals. At predetermined time intervals the relative temporal position of flanks of the first clock and of the second clock representing the transition between two consecutive time-stamps is recorded. From the change in the relative temporal position of the transition flanks of the first clock and of the second clock a correction factor representing the time deviation between the first clock and the second clock is determined. Using the correction factor representing the time deviation between the first clock and the second clock the clock rate of the second clock is readjusted in the sense of a diminution of the time deviation between the first clock and the second clock. The recording, determination and readjustment are repeated.
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Heinrich Werner
Weitl Andreas
Crowell & Moring LLP
EADS Deutschland GmbH
Perveen Rehana
Yanchus, III Paul
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