Process for the thin etching of substrates

Details Process for the thin etching of substrates Process for the thin etching of substrates

1993-03-05

1994-01-18

Powell, William

Harvesters

Cutting, conveying and binding

High outside binder

156643, 156657, 156662, 156646, H01L 21306, B04C 122, C03C 1500, C03C 2506

Patent

active

052797031

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

The present invention refers to a process for the thin etching of substrates which are adapted to be etched by chemical etching agents to an at least areawise uniform, predeterminable substrate layer thickness.
Quite generally, the present invention deals with a process for producing extremely thin substrates or extremely thin substrate layers having layer thicknesses in the order of less than one micrometer.
In the development and in the production of highly-integrated circuits, techniques for providing mutual lateral in a planar mode of arrangement on the semiconductor surface, have increasingly been used within the last few years for reducing the mutual distance between the individual components and for increasing thus the integration density of the integrated circuit. Typical insulation techniques for the mutual lateral insulation of semiconductor components within semiconductor circuits are known to the person skilled in the art under the names of LOCOS as well as trench etching technique.
The reason for the use of lateral insulation techniques is to be seen in the fact that electrically relevant processes in semiconductor circuits typically take place in a region of the semiconductor crystal which defines the uppermost layer region and which has a thickness of approx. 1 .mu.m. For mechanical reasons, it is normally necessary that the semiconductor crystal must have a thickness of many hundred .mu.m. Except for its mechanical carrier function, the thick semiconductor crystal material proves to be disadvantageous with respect to its electrical properties. In comparison with such thick semiconductor crystals, thin substrates have some technological advantages comprising, compared with thicker materials, a simpler lateral insulation by means of which a latch-up effect can be suppressed in the case of CMOS circuits, as well as the absence of extensive space charge regions.
For a prolonged period of time, attempts have been made to utilize the advantages of such thin substrates by means of various techniques, each of said techniques making use of a thin semiconductor layer or usable layer arranged above an insulation layer, which, in turn, is located on a carrier substrate.
One of these techniques is the so called SOS (silicon on sapphire) technique in the case of which a silicon layer is heteroepitactically grown onto a sapphire crystal. However, this technique can only be used for producing silicon layers having a poor crystal quality.
The SIMOX (silicon implanted oxygen) technique comprises the step of implanting high doses of oxygen in silicon, and, after a temperature step, said implanted oxygen will form a buried, insulating SiO.sub.2 layer at a distance of approximately 0.2 .mu.m below the semiconductor surface. This process for producing the buried, insulating layer will, however, cause crystal damage.
The techniques referred to hereinbefore also comprise the so called ZMR (zone melting recrystallization) technique. In the case of this technique an amorphous or microcrystalline silicon layer is first deposited on an oxidized wafer. By means of laser beams or electron beams, the amorphous silicon layer is remelted in its surface region so as to produce large crystal regions. This technique does, however, not offer the possibility of forming the whole recrystallized layer as a single crystal of high quality.
A promising method of producing the above-mentioned SOI substrates, in the case of which the semiconductor layer is located above an insulating layer, is the wafer bonding technique, since with the aid of this technique it is, in principle, possible to produce perfectly monocrystalline usable layers. This technique includes the step of combining the polished surfaces of two wafers under extremely dustfree conditions. Normally, one wafer or both wafers are provided with a silicon dioxide layer, which is produced by thermal oxidation or by deposition of an oxide layer. This oxide layer can also be doped, and it may, for example, include borosilicate glass, phosphorus silicate glass or

REFERENCES:
patent: 2841477 (1958-07-01), Hall
patent: 3830665 (1974-08-01), Roman et al.
patent: 4518456 (1985-05-01), Bjorkholm
patent: 4678536 (1987-07-01), Murayama et al.
patent: 4838989 (1989-06-01), Ashby et al.
patent: 4861421 (1989-08-01), Bienstock
patent: 5057184 (1991-10-01), Gupta
Hodgson, R. T., "Method of Etching Undoped Regions of a Substrate Without sking", IBM Tech. Discl. Bulletin, vol. 23, No. 3, Aug. 1980.
Li, Yu-Lin et al., "Molecular beam study of laser-induced chemical etching of Si(111) by chlorine molecules", Appl., Phys. Lett 53 (20), Nov. 14, 1988, pp. 1955-1957.
Tucker, A. W. et al., "Laser Chemical Etching of Vias in GaAs", IEEE Electron Device Letters, vol. EDL-4, No. 2, Feb. 1983.
von Gutfeld, R. J. et al., "Laser enhanced ething in KOH", IBM Thomas J. Watson Research Center, N.Y., accepted for pub. Nov. 23, 1981.
Harendt, Christine et al., "Silicon-on-Insulator Films Obtained by Etchback of Bonded Wafers", J. Electrochem. Soc., 136/11, Nov. 1989.
Haisma, Jan et al., "High-Quality SOI by Bonding of Standard SI Wafers and Thinning by Polishing Techniques Only", Japanese Journal of Applied Physics, vol. 28, No. 5, May 1989, pp. 725-726.
Bunkin, F. V. et al., "Si Etching Affected by IR Laser Irradiation", Applied Physics, A 37, 1985, pp. 117-119.
Haisma, J. et al, "Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations", JP Journal of Applied Physics, vol. 28, No. 8, Aug. 1989, pp. 1426-1443.

Affiliated with

Also associated with

Rating

Process for the thin etching of substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for the thin etching of substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the thin etching of substrates will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1134076