Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-06
2005-12-06
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06973637
ABSTRACT:
The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.
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Chu Jerome
Moucheron Matthew
Roby Mary
Sharpe John M.
Agere Systems Inc.
Lin Sun James
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